This article presents a case study involving flash memory bit failures characterized by threshold voltage changes due to positive gate disturb stress. An inconsistency in failing bit behavior, which was found to be dependent on the test mode, was explored to provide an electrical explanation for the failure. The underlying defect was isolated and subsequently identified by physical analysis.

This article is the first in a two-part series analyzing solder connection failures between BGA packages and PCB assemblies. Part I examines failures attributed to oxygen intrusion during reflow, underetched solder resist, and solder paste printing problems. In the latter case, X-ray inspection revealed no abnormalities other than a variation in ball size. To get to the root cause, the corpus of the BGA was progressively ground away, leaving only the balls and an unobstructed view of the PCB surface. A description of the process, supported by detailed images, is included in the article. In Part II, scheduled for the May 2017 issue of EDFA, the author delves deeper into the analysis of voids and presents an alternate FA approach that involves grinding away much of the PCB.

Probing in the sub-100 nm realm requires new tools and techniques that are relatively easy to learn if users follow the advice of the authors of this article. The authors present a probing method based on scanning probe technology and demonstrate its use on a 90-nm transistor failure due to a poly-silicon gate short. They also address challenges associated with sample preparation, probe tip contamination and wear, and the effects of vibration and drift.

Single contact optical beam induced currents (SCOBIC) is a variation on the OBIC failure analysis technique that requires only one point of contact with the junction being examined. This article discusses the basic principles of this new method and how it compares with OBIC in terms of measurement performance. It also presents examples showing how SCOBIC can be used to analyze CMOS devices from the front and back side without need for complex FIB and microprobing procedures.

During a silicon debug, it was found that the gain of a radio receiver circuit dropped dramatically at certain frequencies due to an imbalance in one of the signal paths. A metal fix was proposed, but consensus could not be reached on how to validate it because of the difficulty of the FIB edit required and the inherent uncertainty of the approach. In this article, the authors explain how they came up with an alternative approach that proved to be faster, more reliable, and easier to validate than the cut-and-join fix initially proposed. They describe each step of the analog circuit editing process, explaining how they deposit, characterize, and connect matched resistors using focused ion beam techniques.

This article discusses sample preparation challenges that have impeded progress in producing bias-enabled TEM samples from electronic components, as well as strategies to mitigate these issues.

Weak open contacts are common in DRAM cell arrays where they act as a resistance between the cell capacitor and wordline transistor. This article discusses the role of weak open contacts in DRAM failures, the factors that influence their effect on read and write operations, and the complexities involved in assessing potential problems.

Designing circuit edits at the contact level offers tremendous advantages in reliability and yield success over similar edits designed in the metal stack. To that end, a full-thickness backside circuit edit strategy has been developed that eliminates part thinning and promotes the implementation of all edits at the contact level to avoid milling into the metal layers. This article describes the FIB-based circuit edit process and presents several case studies demonstrating its use on 65 nm technology devices.

There is a little known failure mechanism that affects dc coils, particularly those used in low-side-switched circuits. This mechanism involves electrolytic transport of copper from the winding in conjunction with chemical corrosion. For this phenomenon to occur, several conditions must exist simultaneously. This article discusses the conditions under which such failures occur and explains how to minimize their effects if not prevent them.

Engineers at Sandia National Laboratories have developed a technology that may bring down the cost and improve the efficiency of photovoltaic energy conversion. Here they explain how they manufacture photovoltaic modules containing as many as 100,000 silicon solar cells using conventional IC fabrication and PCB assembly techniques. They also explain how they estimate module efficiency based on the IV characteristics of individual cells and the detection of open and short circuits.

Failure analysis labs are fairly well equipped for dealing with shorts and leakages in stacked-die packages, but are at a disadvantage when it comes to opens, particularly those at the die or die interconnect level. This article presents a new FA technique that has the potential to make up for this shortcoming. The new method, called space domain reflectometry (SDR), is based on radio-frequency magnetic current imaging, and as the authors show, is capable of accurately locating a dead open in a double-stacked BGA package, even when the full stack is encapsulated in molding compound.

The ability to discern the composition and placement of atoms in a sample makes TEM one of the most powerful characterization tools for microelectronic components. For many devices, however, the dynamics underlying normal operation do not displace atoms. Device function is, instead, mediated by electronic and thermal processes that have little effect on physical structure, necessitating additional tools to determine the causes of failure. In this article, the author presents results indicating that STEM EBIC, with the new SEEBIC mode, can provide electronic contrast that complements the physical-based contrast of STEM imaging. By identifying device features at higher risk of failure, the two methods may open a path to predictive failure analysis.

This editorial discusses the emergence of chiplets and its potential impact on IC design, fabrication, and failure analysis.

Scanning TEM electron beam-induced current (STEM EBIC) imaging is a promising technique for providing high-resolution electronic and thermal contrast as a complement to TEM’s physical contrast. This article presents recent progress in using the focused ion beam (FIB) to prepare thin, electrically contacted cross-section samples for STEM EBIC imaging and in situ biasing. Techniques involving both standard Ga+ FIB and Xe+ plasma FIB (PFIB) are described.

A recent trend in semiconductor failure analysis involves combining the use of different tools and techniques in order to acquire more accurate data at a faster rate. This article describes a new workflow that combines FIB, GIS, and nanoprobing, all performed at the same FIB tilt position. It also provides two examples in which the workflow is used.

This article reviews the basic failure modes of surface-mount tantalum capacitors and the methods used to determine the cause. It discusses the factors that contribute to leakage, shorts, opens, and high series resistance, the characteristics of each failure mode, and the best approaches for failure analysis.

This article examines current research into the building blocks of the nanoscale system and the techniques used to synthesize them. Also explored are some proposed ideas and the challenges associated with integrating these building blocks into molecular nanosystems such as chemically assembled electronic nanocomputers (CAENs).

Dry tantalum electrolytic capacitors are widely used in electronic equipment because they have high capacitances at useful working voltages, low effective series resistances, relatively long life, and a small footprint. Tantalum capacitors have some limitations as well that, if not taken into account during circuit design, may produce catastrophic failures. The effect of one such limitation is highlighted in this detailed and well-illustrated case study.

Laser-assisted copper deposition provides a key technology for analyzing complex packaging and integrated circuit challenges. Laser-based copper deposition techniques have been shown to be useful in combination with traditional FIB techniques to improve resistivity, deposition rate, and timing.

This article demonstrates the strengths and limitations of electrical testing for locating defects that contribute to contact failures in DRAMs. It presents three case studies, the first of which involves a write problem to a pair of cells that share an open bitline contact. The second case, a read problem between the primary and secondary sense amplifiers, serves as an example of how failure bitmaps and electrical characterization work together to detect and locate defects. The third case is a decoder problem that required additional testing and internal probing in order to determine the location of the defect.