Search Results for reliability testing

This article describes two accelerated reliability tests that can help shorten product development cycles for power semiconductor packages. One test simulates the effects of temperature cycling by applying a series of thermal shocks to the test sample. The other test assesses the bond between metals and molding compounds as a measure of thermal cycle resistance. A button shear test is used to measure changes in adhesion strength as a function of time and temperature.

The goals of the workshop were twofold: Give NIST researchers an industry perspective and evaluate the CHIPS Act Metrology R&D program industry relevance to plan to future projects. This guest editorial provides a brief overview of the February 2024 workshop and its outcomes.

This column explains that in order for supply chain partners to optimize quality and end-to-end yield, progress must be made in the areas of embedded instrument standards, test access mechanisms, and traceability.

The reliability of a component is the probability that it will perform its function under specified conditions for a specified length of time. Key considerations in defining and designing reliability tests are reviewed in this article, which also discusses the interpretation of test results.

Although plastic-encapsulated packaging dominates most of the IC industry, deprocessing and reliability testing continue to be a problem, particularly in industries making the switch from hermetically sealed ceramic packages. This article discusses the challenges designers and failure analysts face in the military and aerospace electronics industry stemming from the use of plastic packages. It provides examples of the types of failures encountered and describes the procedures used to detect and identify them.

This article provides a summary of the ISTFA 2011 Panel Discussion, which centered on the challenge of finding ever-smaller defects in semiconductor devices.

This article assesses the progress that has been made in the development and implementation of through-silicon via (TSV) technology, the work yet to be done, and the challenges associated with potential failure mechanisms.

IBM engineers recently conducted a study to better understand and control the reliability of copper pillar solder joints in 2.5-D packages. Here they describe their approach and the results they obtained. They explain how they created test samples to evaluate different solder compositions, pillar geometries, and thermal histories and assess their effect on microstructure, precipitate morphology, intermetallic layer thickness, and shear strength. They also present thermal cycling test results comparing the performance of silicon and glass interposers.

The failure of a white LED backlight module in a portable computer illustrates the challenges that component and system suppliers must overcome in order to determine root-cause failure mechanisms and take corrective actions that address the problem.

The Package Innovation Roadmap Council (PIRC) was established as part of the Failure Analysis Technology Roadmap activity at the direction of the EDFAS Board. This column provides an overview of a technical paper by the PIRC that highlights recent innovations, technology gaps, and future development trends in package fault isolation and failure analysis. The paper focuses on three main categories: 1) Artificial intelligence (AI) applications, 2) Sample handling, and 3) FA tool robustness.

This article discusses the latest trends in wire bonding and examines common failure mechanisms.

This article presents a method for determining the integrity of solder joints made from mixed and lead-free solders. It discusses the procedures involved in sample preparation and testing and explains how to interpret the results, particularly the effect intermetallic formation, cracking, and voiding.

Government and military ICs, like their commercial counterparts, are subject to ever-tightening cost, performance, and time-to-market demands. They must also comply with strict lifetime, reliability, and radiation hardness standards. In dealing with these challenges for internal applications, engineers at Sandia National Laboratories developed a radiation-hardened structured ASIC platform. In this article, they describe the design and development of the platform and the associated challenges for FA and test.

Traditional post-fabrication testing can reliably verify whether or not an IC is working correctly, but it cannot tell the difference between an authentic and counterfeit chip or recognize design changes made with malicious intent. This article presents an IC decomposition workflow, based on FA tools and techniques, that provides a quantifiable level of assurance for components in a zero trust environment.

Stress voiding is an insidious IC failure mechanism that can be difficult to identify and arrest. It is of particular concern to those who produce and test ICs with aluminum-alloy interconnects or who assess the reliability of legacy devices with long service life. This article explains how stress voids form and grow and how to determine the root cause by amassing physical evidence and ruling out other failure mechanisms. The key to differentiating stress voiding from other types of failures is recognizing that is the result of three distinct physical phenomena, stress, nucleation, and diffusion, all of which must be confirmed before attempting to make process corrections.

The International Symposium for Testing and Failure Analysis (ISTFA) is the premier event for scientists and engineers who work to evaluate failures and improve the performance and reliability of semiconductor devices and processing techniques. This editorial is a look back at ISTFA over the years from the first gathering in 1975. It includes a table listing the ISTFA general chairs for each annual symposium.

Over the last few years, new challenges increased the pressure on packaging and assembly analytical resources. Reduced product development cycle time, increased market segmentation, new package and die level materials, ever shrinking device geometries, and fully enabled technologies (i.e. with thermal, retention, and EMI solutions) created these new pressures on fault isolation/failure analysis efforts and package development.

This article discusses the setup and use of thermoreflectance imaging, a thermal mapping technique with a spatial resolution in the submicron range and a time resolution down to tens of nanoseconds. It describes the basic physics of thermoreflectance measurements and the advantages and limitations of the approach. It also provides examples showing how thermoreflectance imaging is used for thermal characterization, design optimization, and reliability analysis of high-power transistors, electrostatic discharge devices, and copper vias.

Experiments to assess microelectromechanical systems (MEMS) test their functionality and materials properties. These experiments provide knowledge and insight into MEMS failure modes and potential pathways to improve the lifetime of MEMS devices. This article demonstrates the use of optical microscopy and SEM analysis to determine various causes of failure in MEMS devices.

Failure analysis is the study and presentation of observable or measurable phenomena. Risk assessment, on the other hand, is when root causes are studied to predict the potential for future failures. In this article, the author describes a structured problem-solving approach that consists of failure analysis, risk assessment, and advanced modeling. A case study is also presented in which the probability of future failures, due to a delamination defect, is determined based on field returns.