The ratio of good to bad die on a production wafer can range from less than 10% to well over 90%, depending on the process and the complexity of the design. This article provides an overview of the modeling approaches used to predict wafer yield. It explains how to account for relative circuit complexity, systematic and random defects, and defect clustering. As the examples in the article show, with just a basic understanding of yield models, readers can estimate expected yield losses and identify abnormal yield results for a given design.

Layout sensitivity, a measure of vulnerability to yield loss, typically takes several days to compute for a modern VLSI design. In this article, the authors present and demonstrate a new stochastic model that can significantly expedite the process. The model is based on simple IC layout parameters including wire width, wire spacing, and channel density. The authors explain how they derived the model and how it compares to actual data. They also discuss the causes and effects of open and short defects and define the concepts of critical area and layout sensitivity.

Scan-logic diagnosis is used in industry for three main purposes: root-cause analysis, improving manufacturing processes, and improving designs. This article reviews the principles of scan-logic diagnosis and its applications in each of the three areas. It also discusses ongoing challenges and emerging approaches.

This article examines the phenomenon of time-dependent dielectric breakdown (TDDB) in ultrathin gate oxide films and explains why it is no longer considered a catastrophic failure in MOSFET-containing ICs.

This article describes a yield-driven approach for characterizing IC logic failures at the wafer level and presents several case studies to demonstrate its versatility and assess its value.

This case study compares the FA success rate and turn-around time of traditional logic-only and true layout-aware scan diagnosis. It discusses the basic process flow, identifies key success factors, and evaluates physical FA and diagnostic test results obtained from six dies randomly selected from a 9.8 M-gate, seven-metal-layer ASIC manufactured in 90 nm technology. As shown, layout-aware diagnosis reduces the defect search area on the die, in some cases, by an order of magnitude, providing the means to diagnosis-driven yield improvements.

Transmission electron microscopy (TEM) plays an important role semiconductor process development, defect identification, yield improvement, and root-cause failure analysis. At the same time, however, certain artifacts of specimen preparation and imaging present barriers for linear scaling of TEM techniques. This article assesses these challenges and explains how electron tomography is being used to overcome them.

This is the second article in a two-part series that explains how to measure the performance of solid immersion lenses (SILs) used for backside imaging and analysis. In Part I, published in the February 2015 issue of EDFA , the authors describe how they modified a frontside metrology target and used it to evaluate a SIL in a backside imaging system, which prompted the development of an unmounted, backside-specific version of the through-silicon target. In Part II, they explain how these new targets, in addition to measuring resolution, are being used to determine the field of view as well as the line spread and edge response of backside imaging systems. They also discuss some of the challenges encountered when using the targets to characterize emission microscopy systems.

ICs designed for portable devices often make use of reverse-body bias (RBB) modes to limit leakage currents. The added complexity of RBB support circuitry presents a challenge during IC characterization and debug. This article discusses the nature of the problem and explains how to identify irregularities in circuits operating in the body-biased condition using standard debug tools with simple modifications. It describes some of the bugs discovered in an actual examination and explains how they were diagnosed by analyzing I-V curve traces and infrared emission microscopy (IREM) images.

A guest columnist shares some of the lessons learned in the course of his career. The wisdom contained in these lessons can be summed up as follows: look at the problem from different perspectives, believe the data, and don’t give up too soon.