This article shows how 3D XRM can be applied to nondestructively detect non-optimized assembly processes that can influence local stresses and overall device reliability. This makes it useful for process development and failure analysis. When used along with AI training models, 3D XRM can achieve analysis of highly integrated packaging structures with reasonable throughput for process validation and error correction guidance.

During a silicon debug, it was found that the gain of a radio receiver circuit dropped dramatically at certain frequencies due to an imbalance in one of the signal paths. A metal fix was proposed, but consensus could not be reached on how to validate it because of the difficulty of the FIB edit required and the inherent uncertainty of the approach. In this article, the authors explain how they came up with an alternative approach that proved to be faster, more reliable, and easier to validate than the cut-and-join fix initially proposed. They describe each step of the analog circuit editing process, explaining how they deposit, characterize, and connect matched resistors using focused ion beam techniques.

Faster time-to-production of a new product is the common goal of design houses and foundries. This article demonstrates how foundries can contribute through post silicon validation, which allows design houses to focus on more complicated issues.

Traditional post-fabrication testing can reliably verify whether or not an IC is working correctly, but it cannot tell the difference between an authentic and counterfeit chip or recognize design changes made with malicious intent. This article presents an IC decomposition workflow, based on FA tools and techniques, that provides a quantifiable level of assurance for components in a zero trust environment.

Root-cause analysis and FA work hand-in-hand to identify the source of a problem, gather relevant data, and resolve the issue. However, even experienced professionals can succeed in FA while failing in the outcome. This article explains how to avoid common traps, dead ends, and faulty thought processes in the search for root causes.

Further development of SEM-based feature extraction tools for design validation and failure analysis is contingent on reliable sample preparation methods. This article describes how a delayering framework for 130 nm technology was adapted and used on a 45 nm SPI module consisting of 11 metal layers, 10 via layers, two layers of polysilicon, and an active silicon layer. It explains how different polishing and etching methods are used to expose each layer with sufficient contrast for SEM imaging and subsequent feature extraction. By combining polygon sets representing each layer, the full design of the device was reconstructed as shown in one of the images.

This article provides a summary of each of the four User’s Group meetings that took place at ISTFA 2011. The summaries cover key participants, presentation topics, and discussion highlights from each of the following groups: Group 1, Focused Ion Beam; Group 2, 3D Packaging and Failure Analysis; Group 3, Finding the Invisible Defect; and Group 4, Nanoprobing and Electrical Characterization.

This column discusses the potential benefits of developing a dedicated synchrotron-based tool suite for advanced, high-throughput characterization, deprocessing, and validation of ICs.

This article provides an introduction to focused ion beam (FIB) circuit editing, covering the basic process along with best practices and procedures.

This article discusses recent improvements in FIB circuit edit as well as general uses and optimization techniques.

This article describes a proposed novel metric to furnish chip designers with a prognostic tool for x-ray imaging in the pre-silicon stage. This metric is fashioned to provide designers with a concrete measure of how visible the fine-pitched features of their designs are under x-ray inspection. It utilizes a combination of x-ray image data collection, analysis, and simulations to evaluate different design elements.

This paper describes a methodology for preparing contoured devices by using a milling machine in conjunction with a spectral reflectance measurement system for meeting ±5 μm remaining silicon thickness (RST) tolerances.

Lock-in thermography (LIT) is a widely used nondestructive tool for detecting the failure location in integrated circuits. The image pattern recognition algorithm for detecting LIT hotspots benefits image processing and can be leveraged to automate failure analysis processes.

Single contact optical beam induced currents (SCOBIC) is a variation on the OBIC failure analysis technique that requires only one point of contact with the junction being examined. This article discusses the basic principles of this new method and how it compares with OBIC in terms of measurement performance. It also presents examples showing how SCOBIC can be used to analyze CMOS devices from the front and back side without need for complex FIB and microprobing procedures.

Deprocessing of ICs is often the final step for defect validation in FA cases with limited fault-isolation information. This article presents a workflow for deprocessing ICs from the backside using automated thinning and large-area plasma FIB delayering. Advantages to this approach include a reduction in manual planarization and depackaging and a higher degree of precision and repeatability.

This case study compares the FA success rate and turn-around time of traditional logic-only and true layout-aware scan diagnosis. It discusses the basic process flow, identifies key success factors, and evaluates physical FA and diagnostic test results obtained from six dies randomly selected from a 9.8 M-gate, seven-metal-layer ASIC manufactured in 90 nm technology. As shown, layout-aware diagnosis reduces the defect search area on the die, in some cases, by an order of magnitude, providing the means to diagnosis-driven yield improvements.

The Assembly Analytical Forum (AAF) is an organization under the auspices of the Sematech Quality Council. The AAF charter is to develop Packaging Analytical Roadmaps five to ten years into the future that are consistent with the International Technology Roadmap for semiconductors (ITRS). At ISTFA 2003, the AAF will convene with interested conference attendees to review, edit, and validate a white paper that will quantify critical gaps in the current suite of test, measurement, and characterization tools used in the semiconductor industry and provide recommendations on how to address them. The intent is to update the document biannually and review it in numerous industry venues to ensure its relevancy and utility. This article is somewhat of a preview to the Rev 0 AAF white paper.

The presence of copper layers separated by low-k dielectrics in today’s ICs is a major problem for circuit edit engineers. This article explains why and presents a solution that addresses the challenges CE engineers face. According to the authors, the difficulties are primarily due to the interaction of the ion beam with variations in copper grain orientation, the effects of halogen corrosion, and the presence of CuF. As a result, copper milling tends to be uneven and edit times tend to be quite long. The solution presented is based on a chemically-assisted milling and etching process that quickly and uniformly removes copper and dielectric layers while maintaining planarity.

Nanoprobing of transistors and resistors is increasing in importance for both design debug and electrical fault isolation. It is thus necessary to understand the impact of scanning a resistor or transistor with an electron beam in order to draw valid conclusions from nanoprobe measurements. In this article, the authors show that exposing samples to electron beams with energies above 4 keV can change the value of diffusion resistors by as much as 30% and that changes can occur at even lower voltages in areas of the sample covered with less material. The article also sheds light on why the changes occur.

This column suggests that developing 3D structural models as tools for observing and exploring failures in the virtual domain could prove instrumental in avoiding failure without committing hardware. Likewise, instead of building hardware to systematically evaluate failures in the presence of random effects, virtualization through a 3D model could provide a completely user-defined environment for conducting controlled experiments. In such a virtual environment, systematic and random behaviors can be introduced and parsed to provide greater clarity in the search for root causes of failure.