Search Results for preferential etch

A new preferential etch for (100) and (111) oriented, p- and n-type silicon has been developed. This article describes the basic chemistry of the etching process and provides examples of how it defines critical features such as oxidation-induced stacking faults, dislocations, swirl, and striations with minimum surface roughness and pitting. A relatively slow etch rate of around 1 μm/min at room temperature provides etch good control and a long shelf life allows the solution to be stored in large quantities.

A brief look at the roots of ISTFA, the International Symposium for Testing and Failure Analysis.

Silicon pipeline defects are a growing concern in semiconductor manufacturing with no proposed methodology on how to effectively analyze them and separate the underlying causes. In light of this need, a study was conducted using complementary FA techniques to examine these unusual silicon crystal defects and gain a better understanding of their signature characteristics and their effect on device failure. This article, authored by the lead investigator, describes the tests that were performed and presents relevant findings and theories on the factors that contribute to "pipeline" and how they can be controlled. It also presents guidelines for distinguishing between pipeline and dislocation defects and explains how they are related.

Several failure analysis case studies have been conducted over the past few years, illustrating the importance of preserving root-cause evidence by means of artifact-free decapsulation. The findings from three of those studies are presented in this article. In one case, the root cause of failure is chlorine contamination. In another, it is a combination of corrosion and metal migration. The third case involves an EOS failure, the evidence of which was hidden under a layer of carbonized mold compound. In addition to case studies, the article also includes images that compare the results of different decapsulation methods.

Further development of SEM-based feature extraction tools for design validation and failure analysis is contingent on reliable sample preparation methods. This article describes how a delayering framework for 130 nm technology was adapted and used on a 45 nm SPI module consisting of 11 metal layers, 10 via layers, two layers of polysilicon, and an active silicon layer. It explains how different polishing and etching methods are used to expose each layer with sufficient contrast for SEM imaging and subsequent feature extraction. By combining polygon sets representing each layer, the full design of the device was reconstructed as shown in one of the images.

This article discusses sample preparation challenges that have impeded progress in producing bias-enabled TEM samples from electronic components, as well as strategies to mitigate these issues.