Xenon plasma focused ion beam specimen preparation is ideal for preparing plan view TEM specimens due to its large-volume-milling capabilities. This article describes concentrated Ar ion beam milling using low energy as a post-pFIB final thinning step of plan view TEM specimens from a phase change memory device. Precise control of specimen thinning is achieved, which results in high-quality specimens with pristine surfaces and a large field of view for TEM characterization.

Plasma focused ion beam (PFIB) systems can generate ion beams with much higher current and are therefore able to remove larger volumes of material at much faster rates while still maintaining precise control of the beam and its milling action. This article explains how the improved performance of PFIB is leading to new applications in delayering, deprocessing, and site-specific failure analysis.

This article discusses sample preparation challenges that have impeded progress in producing bias-enabled TEM samples from electronic components, as well as strategies to mitigate these issues.

Several technology-focused User's Groups met at ISTFA 2014 to discuss current issues and advances in their areas of interest. This article summarizes key discussion points from the Contactless Fault Isolation User's Group, the Nanoprobing User's Group, the Sample Prep/3-D Package User's Group, and the FIB User's Group.

Scanning TEM electron beam-induced current (STEM EBIC) imaging is a promising technique for providing high-resolution electronic and thermal contrast as a complement to TEM’s physical contrast. This article presents recent progress in using the focused ion beam (FIB) to prepare thin, electrically contacted cross-section samples for STEM EBIC imaging and in situ biasing. Techniques involving both standard Ga+ FIB and Xe+ plasma FIB (PFIB) are described.

Packaging integration continues to increase in complexity, driving more samples into FA labs for development support and analysis. For many of the jobs, there is also a need for larger removal volumes, compounding the demand for tool time and throughput. Focused ion beam (FIB) and dual-beam FIB/SEM systems are helping to relieve the pressure with their ability to create site-specific cross sections and to facilitate gate-level circuit rewire and debug. This article reviews the impact of packaging trends on failure analysis along with recent improvements in FIB technology. It also presents examples that illustrate how these new FIB techniques are being applied to solve emerging packaging challenges.

The semiconductor industry has followed Moore’s law in the last four decades. However, transistor performance improvement will be limited, and designers will not see doubling of frequency every two years. The need for increased performance and further miniaturization has driven the development of advanced packaging solutions, such as fan-in wafer-level chip-scale packaging, fan-out wafer-level packaging, wire-bonded stacked dice, and package-on-package. These technologies are used in mass production and provide significant benefits in form factor but may not give the desired improvement in die-to-die bandwidth. Recently, 3-D integrated circuits (ICs) that employ vertical through-silicon vias (TSVs) for connecting each die have been proposed. It is an alternative solution to existing package-on-package and system-in-package processes. This column addresses some of the challenges in implementing new TSV techniques.

Liquid metal ion and plasma beam FIB systems are widely used in the semiconductor industry for TEM lamella preparation, circuit edit, and cross-sectional analysis. This article compares the deprocessing capability of a Ga FIB with that of a Xe plasma FIB. Both systems were used to delayer an Intel 14 nm processor from M8 down to the transistor contacts. As the images in the article show, a 100 × 100 µm window was opened by the Xe plasma FIB and a 20 × 20 µm window was opened with the Ga FIB. Related issues such as processing time, end point detection, and surface roughness are also discussed.

This article provides a summary of the presentations given at the four User’s Group meetings at ISTFA 2012. Each user group focused on one of the following topics: nanoprobing, contactless fault isolation, focused ion beam, and sample preparation.

This article discusses the current state of large area integrated circuit deprocessing, the latest achievements in the development of automated deprocessing equipment, and the potential impact of advancements in gas-assisted etching, ion source alternatives, compact spectroscopy, and high-speed lasers.

Deprocessing of ICs is often the final step for defect validation in FA cases with limited fault-isolation information. This article presents a workflow for deprocessing ICs from the backside using automated thinning and large-area plasma FIB delayering. Advantages to this approach include a reduction in manual planarization and depackaging and a higher degree of precision and repeatability.

The sixth FIB-SEM workshop was held March 1, 2013, in Cambridge, Mass. This article provides a summary of the event along with highlights from the 18 paper presentations.

This article provides a recap and summaries of the EDFAS Virtual User Group Workshop held in January 2021. The summaries cover key participants, presentation topics, and discussion highlights from the Focused Ion Beam, Sample Preparation, Contactless Probing and Nanoprobing, and System on Package virtual group meetings.

Broad ion beam delayering is a versatile technique for whole-chip failure analysis. The large area of uniformity coupled with the ability to precisely stop at the layer of interest facilitates repeatable, rapid defect detection anywhere on the chip.

The presence of copper layers separated by low-k dielectrics in today’s ICs is a major problem for circuit edit engineers. This article explains why and presents a solution that addresses the challenges CE engineers face. According to the authors, the difficulties are primarily due to the interaction of the ion beam with variations in copper grain orientation, the effects of halogen corrosion, and the presence of CuF. As a result, copper milling tends to be uneven and edit times tend to be quite long. The solution presented is based on a chemically-assisted milling and etching process that quickly and uniformly removes copper and dielectric layers while maintaining planarity.

This article discusses the failure analysis challenges associated with large overmolded 2.5D packages and explains how laser decapsulation followed by microwave-induced plasma (MIP) spot etching removes overmold while keeping everything else intact. It also describes a defect isolation procedure in which the sample is analyzed in a large chamber environmental SEM with its ball grid array directly wired to an EBAC amplifier.

This article provides a summary of each of the four User’s Group meetings that took place at ISTFA 2011. The summaries cover key participants, presentation topics, and discussion highlights from each of the following groups: Group 1, Focused Ion Beam; Group 2, 3D Packaging and Failure Analysis; Group 3, Finding the Invisible Defect; and Group 4, Nanoprobing and Electrical Characterization.

The complexity of sample preparation and deprocessing has risen exponentially with the emergence of 2.5-D and 3D packages. This article provides answers and insights on how to deal with the challenges of increasingly complex semiconductor packages. After identifying pressing issues and potential bottlenecks with state-of-the-art FA flows, the authors present two case studies demonstrating the capabilities of electro-optical terahertz pulse reflectometry (EOTPR), plasma FIB milling, and 3D X-ray imaging. The FA results confirm the potential of all three techniques and indicate that a fully nondestructive integration flow for 3D packages may be achievable with further development and optimization.

Further development of SEM-based feature extraction tools for design validation and failure analysis is contingent on reliable sample preparation methods. This article describes how a delayering framework for 130 nm technology was adapted and used on a 45 nm SPI module consisting of 11 metal layers, 10 via layers, two layers of polysilicon, and an active silicon layer. It explains how different polishing and etching methods are used to expose each layer with sufficient contrast for SEM imaging and subsequent feature extraction. By combining polygon sets representing each layer, the full design of the device was reconstructed as shown in one of the images.

Failure analysis is becoming increasingly difficult with the emergence of 3D integrated packages due to their complex layouts, diverse materials, shrinking dimensions, and tight fits. This article demonstrates several FA techniques, including high-frequency scanning acoustic microscopy, lock-in thermography, and FIB cross-sectioning in combination with plasma ion etching or laser ablation. Detailed case studies show how the various methods can be used to analyze bonding integrity between different materials, chip-to-chip interface structures, buried interconnect defects, and through-silicon vias at either the device or package level.