Photon emission microscopy (PEM) has proven to be a powerful tool for fault isolation and has adapted well to ongoing changes in technology and emerging needs. In this tutorial, the authors describe the fundamentals of photon emission, the essential elements of a typical PEM system, and the procedures involved in diagnosing various types of failures. They also classify a wide range of photon-emitting defects and explain how PEM is used for backside analysis of flip-chip packaged devices and for timing diagnostics.

This article presents and evaluates a calibration method that significantly improves the spectral information that can be extracted from photon emission signals obtained from semiconductor devices. Step-by-step instructions are given for calibrating photon emission microscopes for specific measurements such as device parameters and material band gap. The article also discusses the types of errors that can occur during calibration. Although the procedure presented is used on InGaAs sensors, it applies to all common photon emission detectors.

This article provides a high-level review of the tools and techniques used for backside analysis. It discusses the use of laser scanning and conventional microscopy, liquid and solid immersion lenses, photon emission microscopy (PEM), and laser-based fault isolation methods with emphasis on light-induced voltage alteration (LIVA). It explains how laser voltage probing is used for backside waveform acquisition and describes backside sample preparation and deprocessing techniques including parallel polishing and milling, laser chemical etching, and FIB circuit edit and modification.

This article discusses some of the early uses of emission microscopy in semiconductor device failure analysis and the challenges that were overcome to make it the invaluable tool it is today. One of the impediments early on was a misconception that silicon cannot emit light when, in fact, it has several light emission mechanisms that have proven useful in electron microscopy. One such mechanism, avalanche luminescence, occurs in junctions during reverse breakdown and is useful for resolving low breakdown voltage and problems with ESD protection circuits. Other light emission mechanisms discussed in the article include forward bias emission, MOS transistor saturation, and dielectric luminescence, which is used to examine oxide test structures and detect oxide defects.

Researchers at Boston University have made significant improvements in the resolution that can be achieved with backside imaging techniques. In this article, they explain how they optimize lateral and longitudinal resolution of IR-based methods using aplanatic solid immersion lenses in combination with adaptive optics that correct for aberrations, interferometry to improve signal-to-noise ratios, vortex beams that overcome diffraction limitations, and image reconstruction techniques based on prior knowledge about the objects under investigation.

Advancements in photodetector technology are revitalizing time-resolved emission (TRE) techniques in semiconductor failure analysis. In this article, the authors explain how superconducting single-photon detectors improve the capabilities of TRE measurements as demonstrated on 14 nm FinFET technology and an inverter chain with power supply voltages down to 0.4 V.

The 22nd European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF 2011) was held October 3 to 7, 2011, in Bordeaux, France. The conference concentrated on two main areas in electronics that concern designers, manufacturers, and users: (1) strategy for quality and reliability assessment of electronic circuits and systems, and (2) advanced analysis techniques for technology and product evaluation. This article reports on highlights of the technical program.

Selecting a fault isolation technique for a particular type of SRAM logic failure requires an understanding of available methods. In this article, the authors review common fault isolation techniques and present several case studies, explaining how they determined which technique to use.

Backside optical analysis is often aided by solid immersion lenses (SILs), but as the authors of this article explain, SILs improve the resolution of front side thermography as well. The authors describe the physics behind solid immersion lenses and provide examples that demonstrate the advantages and limitations of their use from the font side.

This article describes a yield-driven approach for characterizing IC logic failures at the wafer level and presents several case studies to demonstrate its versatility and assess its value.

Recent advances in spectrometers now give sufficient sensitivity to measure the spectral content of the very weak light emission produced by failing semiconductor devices. This article examines light spectra from the most common defect classes in order to demonstrate the strengths and weakness of spectral analysis in the context of semiconductor failure investigations. The conclusion is that signature analysis may not provide a definitive root cause, but it can help confirm the root cause after further analysis is performed.

This article describes a novel method for improving image resolution achieved using time-resolved photon emission techniques. Instead of directly generating images from photon counting, all detected photons are displayed as a point cloud in 3D space and a new higher-resolution image is generated based on probability density functions associated with photon distributions. Unsupervised learning algorithms identify photon distribution patterns as well as fainter emission sources.

This column identifies promising new failure analysis technologies based on the papers published in recent ISTFA conferences. The purpose of the column is not to select the "best of the best," but rather to understand the technologies that have been developed and adopted to solve the ever-growing challenges in failure analysis.

Technologies relatively new to failure analysis, like time-correlated photon counting, electro-optical probing, antireflective (AR) coating, Schlieren microscopy, and superconducting quantum interference (SQUID) devices are being leveraged to create faster, more powerful tools to meet increasingly difficult challenges in failure analysis. This article reviews recent advances and research in fault isolation and circuit repair.

The semiconductor industry has followed Moore’s law in the last four decades. However, transistor performance improvement will be limited, and designers will not see doubling of frequency every two years. The need for increased performance and further miniaturization has driven the development of advanced packaging solutions, such as fan-in wafer-level chip-scale packaging, fan-out wafer-level packaging, wire-bonded stacked dice, and package-on-package. These technologies are used in mass production and provide significant benefits in form factor but may not give the desired improvement in die-to-die bandwidth. Recently, 3-D integrated circuits (ICs) that employ vertical through-silicon vias (TSVs) for connecting each die have been proposed. It is an alternative solution to existing package-on-package and system-in-package processes. This column addresses some of the challenges in implementing new TSV techniques.

The best spatial resolution that can be achieved with far-field optical fault localization techniques is around 20 times larger than the critical defect size at the 45 nm technology node. There is also a limit on the laser power that can be safely used on 45 nm devices, which further compromises fault localization precision. In this article, the authors explain how they overcome these limitations using pulsed laser-induced imaging techniques and a refractive solid immersion lens. Two case studies show how the combination of pulsed-laser scanning optical microscopy and a solid immersion lens improves localization precision and detection sensitivity.

Off-state leakage currents account for roughly half of the total current is today’s ICs, and with each new generation of technology, the problem is getting worse. Failure analysts, however, see things differently. Light emission associated with leakage current is a rich source of information about the operation of ICs. In this article, the authors explain how they use this light to monitor logic states, measure temperatures, analyze cross-talk and power distribution noise, and diagnose broken scan chains. Light emission from off-state leakage current (LEOSLC) is shown to be especially useful for diagnosing faults that reside in scan clock trees, which are otherwise very difficult to detect.

IDDQ testing is normally the key to isolating state-dependent defects in dense ICs. In the case study presented here, however, the functionally failing ICs did not fail the static IDDQ test nor did they draw significant current when biased into a static state on the lab bench. After extensive testing and analysis, including ATE IDDQ scanning, ATE-interfaced photo-emission microscopy, FIB assisted mechanical microprobing, and scanning capacitance microscopy, the defect was found to be p-type counterdoping of the n-active regions caused by a contaminated solvent tank used during wafer fabrication.

Many standard physical failure site isolation techniques require an electrical stimulus to drive test devices into a failing condition. This function has been provided by bench test electronics for some time, but increasing device complexity is causing a migration to more sophisticated equipment such as pattern generators and logic analyzers. In anticipation of further increases in pin count and density, a new class of small footprint testers is emerging. These portable systems, called ASIC verification testers, facilitate the transfer of ATE test programs to failure analysis laboratories at relatively low cost.

Researchers have developed an imaging technique that reveals wiring defects in packaged ICs without requiring decapsulation. The sensing mechanism is based on resistance changes, similar to IR-OBIRCH, but instead of an IR beam, the metal conductors in the chip are heated by ultrasonic waves. This article describes the basic principles of ultrasonic beam induced resistance change (SOBIRCH) imaging and demonstrates its effectiveness in a wide range of applications, including multilayer metal stacks.