Xenon plasma focused ion beam specimen preparation is ideal for preparing plan view TEM specimens due to its large-volume-milling capabilities. This article describes concentrated Ar ion beam milling using low energy as a post-pFIB final thinning step of plan view TEM specimens from a phase change memory device. Precise control of specimen thinning is achieved, which results in high-quality specimens with pristine surfaces and a large field of view for TEM characterization.

This article describes how physical attacks can be launched on different types of nonvolatile memory (NVM) cells using failure analysis tools. It explains how the bit information stored inside these devices is susceptible to read-out and fault injection attacks and defines vulnerability parameters to help quantify risks associated with different modalities of attack. It also presents an in-depth security analysis of emerging NVM technologies and discusses potential countermeasures.

This article discusses sample preparation challenges that have impeded progress in producing bias-enabled TEM samples from electronic components, as well as strategies to mitigate these issues.

Various NVM technologies are being explored for neuromorphic system realization, including resistive RAM, ferroelectric RAM, phase change RAM, spin transfer torque RAM, and NAND flash. This article discusses the potential of RRAM for such applications and evaluates key performance and reliability metrics in the context of neural network image classification. The authors conclude that the accuracy-power tradeoff may be further improved using alternative material stacks and multi-layer dielectrics so as to achieve better control of the oxygen vacancy or metallic filamentation process that governs RRAM switching characteristics.

Four-dimensional scanning transmission electron microscopy (4D-STEM) is a spatially resolved electron diffraction technique that records the electron scattering distribution at each point of the electron beam raster, thereby producing a four-dimensional dataset. This second installment of this series presents applications of 4D-STEM, including measurements of crystal orientation and phase, short- and medium-range order, and internal electromagnetic fields.

Shmoo plotting began in the early 1970s and still has wide use in characterizing device performance against various parameters. Typically, Shmoo plots measure device frequency or cycle time versus voltage. The debug described in this article focused on problems (holes) in Shmoo plots discovered while designing a 637-MHz microprocessor. This problem had two distinct phases as the microprocessor design migrated from an older CMOS process technology into a newer, faster one. Resolution of the problem, as the article explains, required advanced DFD/DFT (design for debug/design for test) techniques and FIB circuit edit to resolve.

This column assesses the current state and outlook for superconducting device technology and its application in exascale computing.

Wafer-level failure analysis plays an important role in IC fabrication, both in process development and yield enhancement. This article outlines the general flow for wafer-level FA and explains how it differs for memory and logic products. It describes the tools and procedures used for failure mode verification, electrical analysis, fault localization, sample preparation, chemical analysis, and physical failure analysis. It also discusses the importance of implementing corrective actions and tracking the results.

It seems that scaling of chip technology according to Moore’s Law will continue for digital functionalities (logic and memory); however, increasing system integration on chip and package levels, called “More than Moore,” has been observed in the past several years. This strong trend in the worldwide semiconductor industry enables more functionality, diversification, and higher value by creating smart microsystems. This article discusses the many challenges faced in FA of 3-D chips, where well-staffed and equipped FA labs are essential. Furthermore, FA is becoming an important strategic enabling factor for new products, not just another “cost factor.”

This column commemorates the life and career of Jack Kilby, who passed away June 20, 2005. Kilby was the keynote speaker for the 25th anniversary of the ISTFA conference in 1999 and in 2000 was awarded the Nobel Prize in Physics for his part in the invention of the integrated circuit in 1958.

Scan-logic diagnosis is used in industry for three main purposes: root-cause analysis, improving manufacturing processes, and improving designs. This article reviews the principles of scan-logic diagnosis and its applications in each of the three areas. It also discusses ongoing challenges and emerging approaches.

Scanning nonlinear dielectric microscopy (SNDM) is a scanning probe technique that measures changes in oscillation frequency between the probe tip and a voltage-biased sample. As the probe moves across the surface of a semiconductor device, the oscillation frequency changes in response to variations in dielectric properties, charge and carrier density, dopant concentration, interface states, or any number of other variables that affect local capacitance. Over the past few years, researchers at Tohoku University have made several improvements in dielectric microscopy, the latest of which is a digital version called time-resolved SNDM (tr-SNDM). Here they describe their new technique and present an application in which it is used to acquire CV, d C /d V-V , and DLTS data from SiO 2 /SiC interface samples.

Optical second-harmonic generation (SHG) is a noninvasive technique that provides information about interface properties and crystal defects. This article demonstrates the use of SGH in the study of high-k dielectrics, silicon-on-insulator structures, compound semiconductors, and through-silicon vias.

This article describes recent advancements in multi-probe sensing schemes and development of a tomographic atomic force microscopy tool for materials research and failure analysis.

The inverted orientation of a flip-chip packaged die makes it vulnerable to optical attacks from the backside. This article discusses the nature of that vulnerability, assesses the threats posed by optical inspection tools and techniques, and provides insights on effective countermeasures.

Interposers play an important role in 2.5D and 3D packages, routing power and communication signals between dies while maintaining electrical contact with I/O pins. This role and their relatively simple construction makes interposers a target for malicious attacks. In this article, the authors assess the vulnerabilities inherent in the fabrication of interposers and describe various types of optical attacks along with practical countermeasures.

Dealing with timing failures in nanometer-scale ICs requires a deeper understanding of critical timing paths, noise mechanisms, process variability, timing rules, and the statistical interaction of random parameter values and distributions. This article examines the factors that affect nanometer timing at both the component and system level. It reviews the timing properties of nanoscale logic gates, latches, edge-triggered flip-flops, clocks and their interconnects, resistive vias, and pipeline structures. It also discusses the challenges involved in determining critical timing paths and the underlying causes of nanometer timing failures.

This article provides a detailed overview of silicon characterization and debug process, describing the intent of each step, the challenges involved, and the FA tools and techniques used. It also discusses the difference between electrical and functional failures, the implementation and use of on-chip debugging resources, the important role of schmoo plots.

Traditional post-fabrication testing can reliably verify whether or not an IC is working correctly, but it cannot tell the difference between an authentic and counterfeit chip or recognize design changes made with malicious intent. This article presents an IC decomposition workflow, based on FA tools and techniques, that provides a quantifiable level of assurance for components in a zero trust environment.

This column explains why transmission X-ray microscopy (TXM) and X-ray computed tomography (XCT) could become the methods of choice for defect localization in the coming years.