Search Results for patents

This column discusses the effect of changes in the U.S. patent process and explains how they benefit failure analysts. He also relates one of his own experiences with filing for a patent based on an observation he and a colleague made in a semiconductor FA lab.

In this article, the author considers the factors that make an idea patentable and explains where ideas that may lead to patents are likely to originate.

This is the story of how the mainstream Omniprobe FIB lift-out solution was invented and delivered to the market.

The presence of copper layers separated by low-k dielectrics in today’s ICs is a major problem for circuit edit engineers. This article explains why and presents a solution that addresses the challenges CE engineers face. According to the authors, the difficulties are primarily due to the interaction of the ion beam with variations in copper grain orientation, the effects of halogen corrosion, and the presence of CuF. As a result, copper milling tends to be uneven and edit times tend to be quite long. The solution presented is based on a chemically-assisted milling and etching process that quickly and uniformly removes copper and dielectric layers while maintaining planarity.

This column discusses the benefits of using IC design and wafer-processing test data for failure analysis.

Latchup has long been a concern for CMOS technologies and is becoming more of an issue with the reduction of transistor dimensions and spacing. Although many techniques for avoiding the risk of latchup have been developed, they generally apply to specific technologies and are not portable to others. In light of the problem, IBM engineers conducted an in-depth evaluation of the structures most sensitive to latchup ignition and the many possible triggering mechanisms. In this article, they describe the work they performed along with the findings and provide practical guidelines on how to minimize latchup regardless of the IC technology involved.

Magnetic field imaging is proving to be a valuable tool for semiconductor failure analysts and test engineers. One of its main advantages is that it does not require sample preparation or deprocessing because magnetic fields pass through most materials used in ICs and device packages. This article discusses the theory and practical limitations of magnetic field imaging and demonstrates its use in mapping current density and determining the location and depth of current-carrying conductors.

This column provides a ten-year retrospective on laser-based fault isolation techniques and the important role of laser signal injection microscopes.

This article discusses the concept and intent of a construction analysis and the value it provides to manufacturers and users of integrated circuits. It describes the basic steps of a construction analysis for semiconductor devices and presents and interprets measurements and observations obtained from the analyses of several ICs.

IBM engineers have developed a holographic imaging technique, called dual-lens electron holography, that provides high spatial resolution and field of view without compromising signal-to-noise ratio. This article reviews the basic principles of the new method and provides several examples of its use. The first few examples demonstrate the junction profiling capabilities of the new method which, in one case, helps to explain why shallow junction devices are made with raised source-drain regions. In the other examples, dual-lens holography is used for strain mapping, in one case, to study strain distributions in sigma-shaped SiGe devices, and in another, to provide evidence that stress memorization occurs in dislocations in the source-drain region of nFET devices.

Modified Talbot X-ray interferometry provides three contrast modes simultaneously: absorption, phase, and dark field/scattering. This article describes the powerful new imaging technique and shows how it is used to characterize various types of defects in advanced semiconductor packages.

Sample preparation is a critical step for dopant profiling of FinFET devices, especially when targeting individual fins. This article describes a sample-preparation technique based on low-energy, shallow-angle ion milling and shows how it minimizes surface amorphization and improves scanning capacitance microscopy (SCM) signals representative of local active dopant concentration.

Engineers at Sandia National Laboratories have developed a technology that may bring down the cost and improve the efficiency of photovoltaic energy conversion. Here they explain how they manufacture photovoltaic modules containing as many as 100,000 silicon solar cells using conventional IC fabrication and PCB assembly techniques. They also explain how they estimate module efficiency based on the IV characteristics of individual cells and the detection of open and short circuits.

Advancements in photodetector technology are revitalizing time-resolved emission (TRE) techniques in semiconductor failure analysis. In this article, the authors explain how superconducting single-photon detectors improve the capabilities of TRE measurements as demonstrated on 14 nm FinFET technology and an inverter chain with power supply voltages down to 0.4 V.

Ex-situ lift out (EXLO) techniques rely on van der Waals forces to transfer FIB milled specimens to various types of carriers using a glass probe micromanipulator. This article describes some of the latest EXLO techniques for site specific scanning transmission electron microscopy, including the use slotted half-grids and vacuum-assisted lift out for plan-view analysis.

A new and improved sample preparation technique was developed by Wang. This technique uses an FIB instrument for the 90° rotation of a small portion of the specimen on the original grid by taking advantage of static force. All sample preparation steps, including thin-section creation and sample tilting, can be accomplished in a single process. The procedure is monitored in a high-resolution FIB instrument to assure a 100% success rate. Figure 1 shows a scanning electron microscope image of a 3D TEM sample with two rotated sections. The original TEM sample is a lift-out sample laid on carbon film.

This article provides an overview of a commercial 3D X-ray system, explaining how it acquires high-resolution images of submicron defects in large intact samples. It presents examples in which the system is used to reveal cracks in thin redistribution layers, voids in organic substrates, and variations in TSV metallization on 300-mm wafers. As the authors explain, each scan can be done in as little as a few minutes regardless of sample size, and the resulting images are clear of the beam hardening artifacts that often cause problems in failure analysis and reverse engineering.

The Internet of Things concept is the “next big thing,” but what are the obstacles to achieving its potential? This article describes some key challenges with this evolving technology, including device failure, sensitivity, scalability, middleware, and user interaction.

Off-state leakage currents account for roughly half of the total current is today’s ICs, and with each new generation of technology, the problem is getting worse. Failure analysts, however, see things differently. Light emission associated with leakage current is a rich source of information about the operation of ICs. In this article, the authors explain how they use this light to monitor logic states, measure temperatures, analyze cross-talk and power distribution noise, and diagnose broken scan chains. Light emission from off-state leakage current (LEOSLC) is shown to be especially useful for diagnosing faults that reside in scan clock trees, which are otherwise very difficult to detect.

Engineers at IBM’s Watson Research Center are contending with one of the most fundamental limitations of imaging technology: the tradeoff between spatial resolution and field of view. In this article, they explain how they created tool interfaces, control and automation software, and image analysis and stitching algorithms, enabling photon emission and laser scanning microscopes to produce high-resolution mosaic images of advanced processor cores and other large-area ICs. They describe some of the challenges they faced and explain how their technology can be used to create images based on reflected light, induced voltage, photon emission, and laser stimulation signatures. In one of the latest demonstrations, the technology was used to land and focus a SIL more than 4000 times, acquiring some 16,000 images that were composed into stitched mosaics of several hundred images each.