Search Results for parasitic ringing

This article discusses the causes and effects of parasitic ringing in the gate drive circuit of dc-to-dc converters. It also presents experimental results validating a possible solution.

This columnn explores the idea that insights into the root cause of increasingly complex failures may be hidden in unanswered questions from past analyses, indicating that there might be more value in previous files than once thought.

Latchup has long been a concern for CMOS technologies and is becoming more of an issue with the reduction of transistor dimensions and spacing. Although many techniques for avoiding the risk of latchup have been developed, they generally apply to specific technologies and are not portable to others. In light of the problem, IBM engineers conducted an in-depth evaluation of the structures most sensitive to latchup ignition and the many possible triggering mechanisms. In this article, they describe the work they performed along with the findings and provide practical guidelines on how to minimize latchup regardless of the IC technology involved.

This article discusses the challenges involved in testing analog and mixed-signal ICs and provides practical guidance and insights on how to deal with them.

This article presents and evaluates a calibration method that significantly improves the spectral information that can be extracted from photon emission signals obtained from semiconductor devices. Step-by-step instructions are given for calibrating photon emission microscopes for specific measurements such as device parameters and material band gap. The article also discusses the types of errors that can occur during calibration. Although the procedure presented is used on InGaAs sensors, it applies to all common photon emission detectors.

This article provides a detailed overview of silicon characterization and debug process, describing the intent of each step, the challenges involved, and the FA tools and techniques used. It also discusses the difference between electrical and functional failures, the implementation and use of on-chip debugging resources, the important role of schmoo plots.

Dealing with timing failures in nanometer-scale ICs requires a deeper understanding of critical timing paths, noise mechanisms, process variability, timing rules, and the statistical interaction of random parameter values and distributions. This article examines the factors that affect nanometer timing at both the component and system level. It reviews the timing properties of nanoscale logic gates, latches, edge-triggered flip-flops, clocks and their interconnects, resistive vias, and pipeline structures. It also discusses the challenges involved in determining critical timing paths and the underlying causes of nanometer timing failures.

This article provides a high-level review of the tools and techniques used for backside analysis. It discusses the use of laser scanning and conventional microscopy, liquid and solid immersion lenses, photon emission microscopy (PEM), and laser-based fault isolation methods with emphasis on light-induced voltage alteration (LIVA). It explains how laser voltage probing is used for backside waveform acquisition and describes backside sample preparation and deprocessing techniques including parallel polishing and milling, laser chemical etching, and FIB circuit edit and modification.