Failure analysis labs are fairly well equipped for dealing with shorts and leakages in stacked-die packages, but are at a disadvantage when it comes to opens, particularly those at the die or die interconnect level. This article presents a new FA technique that has the potential to make up for this shortcoming. The new method, called space domain reflectometry (SDR), is based on radio-frequency magnetic current imaging, and as the authors show, is capable of accurately locating a dead open in a double-stacked BGA package, even when the full stack is encapsulated in molding compound.

Liquid metal ion and plasma beam FIB systems are widely used in the semiconductor industry for TEM lamella preparation, circuit edit, and cross-sectional analysis. This article compares the deprocessing capability of a Ga FIB with that of a Xe plasma FIB. Both systems were used to delayer an Intel 14 nm processor from M8 down to the transistor contacts. As the images in the article show, a 100 × 100 µm window was opened by the Xe plasma FIB and a 20 × 20 µm window was opened with the Ga FIB. Related issues such as processing time, end point detection, and surface roughness are also discussed.

The complexity of sample preparation and deprocessing has risen exponentially with the emergence of 2.5-D and 3D packages. This article provides answers and insights on how to deal with the challenges of increasingly complex semiconductor packages. After identifying pressing issues and potential bottlenecks with state-of-the-art FA flows, the authors present two case studies demonstrating the capabilities of electro-optical terahertz pulse reflectometry (EOTPR), plasma FIB milling, and 3D X-ray imaging. The FA results confirm the potential of all three techniques and indicate that a fully nondestructive integration flow for 3D packages may be achievable with further development and optimization.

Scanning laser-SQUID microscopy is a new electrical inspection and failure analysis technique that can detect open, high-resistance, and shorted interconnects without electrical contact in areas ranging in size from a few square microns to an entire die. This article describes the setup of a prototype laser-SQUID system, explaining how it works and how it compares to other nondestructive defect localization techniques. It presents application examples in which laser-SQUID microscopy is used to locate gate oxide shorts to within 1.3 μm and detect IC defects prior to bond-pad pattering and after bonding and packaging. It also includes a series of images acquired from a board-mounted chip with fields of view ranging from 5 x 5 mm down to 50 x 50 μm.

Recent developments in two relatively new failure analysis techniques, Seebeck effect imaging (SEI) and thermally-induced voltage alteration (TIVA), have greatly improved their defect detection sensitivity and image acquisition times for localizing open and shorted interconnections. This article presents several examples demonstrating the enhanced capabilities of these two methods.

This article demonstrates the strengths and limitations of electrical testing for locating defects that contribute to contact failures in DRAMs. It presents three case studies, the first of which involves a write problem to a pair of cells that share an open bitline contact. The second case, a read problem between the primary and secondary sense amplifiers, serves as an example of how failure bitmaps and electrical characterization work together to detect and locate defects. The third case is a decoder problem that required additional testing and internal probing in order to determine the location of the defect.

This article discusses the causes and effects of stuck-open faults (SOFs) in nanometer CMOS ICs. It addresses detection and localization challenges and explains how resistive contacts and vias and the use of damascene-copper processes contribute to the problem. It also discusses layout techniques that reduce the likelihood of SOF failures.

Engineers at Sandia National Laboratories have developed a technology that may bring down the cost and improve the efficiency of photovoltaic energy conversion. Here they explain how they manufacture photovoltaic modules containing as many as 100,000 silicon solar cells using conventional IC fabrication and PCB assembly techniques. They also explain how they estimate module efficiency based on the IV characteristics of individual cells and the detection of open and short circuits.

Scanning probe microscopy (SPM) is widely used for fault isolation as well as diagnosing leakage current, detecting open circuits, and characterizing doping related defects. In this article, the author presents two SPM applications that are fairly uncommon but no less important in the scope of failure analysis. The first case involves the discovery of nano-steps on the surface of high-voltage NFETs, a phenomenon associated with stress-induced crystalline shift along the (111) silicon plane. In the second case, the author uses an AFM probe in the conductive mode to correlate tunneling current distribution with hot spots in high-k gate oxide films, which is shown to be a better indicator of oxide quality than rms surface roughness.

CMOS IC failure mechanisms are of three general types: bridge defects, open circuit defects, and parametric related failures. This article summarizes bridge and open-circuit defect properties and provides references for further self-study. Bridge defects are characterized based on location, their significance in terms of logic gates and transistors, and critical resistance for dc logic and timing failures. Open defects are more complex and diverse with six possible failure modes each of which are described in the article.

A wide range of electrical faults are revealed through thermal laser stimulation (TLS). In principle, an electrical parameter, typically current or voltage, is monitored for changes caused by the heating effects of the laser. Most test setups are designed to limit the activity of the device in order to minimize the signal-to-noise ratio, but in some cases, the fault’s electrical footprint can only be detected when the device is stimulated in a dynamic way. This article describes the setup and implementation of various dynamic TLS methods and presents example applications demonstrating the advantages and limitations of each approach.

One of the pioneering developers of induced voltage alteration (IVA) measurement techniques assesses the current state of the technology, the impact of major advancements, and the potential for further improvements. The assessment pays particular attention to biasing approaches, phase-locked loop detection techniques, the effect of solid immersion lenses on spatial resolution, and the emergence of production-type sample preparation methods.

Weak open contacts are common in DRAM cell arrays where they act as a resistance between the cell capacitor and wordline transistor. This article discusses the role of weak open contacts in DRAM failures, the factors that influence their effect on read and write operations, and the complexities involved in assessing potential problems.

This article provides a qualitative overview of several new defect localization techniques, including charge-induced voltage alteration (CIVA), light-induced voltage alteration (LIVA), thermally-induced voltage alteration (TIVA), and Seebeck effect imaging (SEI). It explains how each method works in terms of the physics of signal generation and the types of images they produce. It also includes a summary highlighting the similarities and differences of each technique.

Chip-level 3D integration, where chips are thinned, stacked, and vertically interconnected using TSVs and microbumps, brings as many challenges as it does improvements, particularly in the area of failure analysis. This article assesses the capabilities of various FA techniques in light of the challenges posed by 3D integration and identifies current shortcomings and future needs.

A team of semiconductor engineers recently developed a new fault localization method tailored for high-resistance faults. In this article, they discuss the basic principle of the technique and explain how they validated it for various test cases.

One of the co-chairs of the Case Histories sessions at ISTFA 2012 provides a summary of three papers that demonstrate a solid understanding of the semiconductor FA process. The first paper describes the investigation of fractures in PCB traces, the second paper presents a method for analyzing defects due to implanter charging effects, and the third paper explains how analysts determined the cause of automatic test pattern generation failures concentrated in certain areas of the wafer.

Magnetic current imaging provides electrical fault isolation for shorts, leakage currents, resistive opens, and complete opens. In addition, it can be performed nondestructively from either side a die, wafer, packaged IC, or PCB. This article reviews the basic theory and attributes of MCI, describes the types of sensors used, and discusses general measurement procedures. It also presents application examples demonstrating recent advancements and improvements in MCI.

This article discusses the advantages of SEM-based nanoprobing and the various ways it can be used to locate defects associated with IC failures. It describes the basic measurement physics of electron beam induced current, absorbed electron, and voltage distribution contrast imaging and presents examples showing how the different methods are used to isolate low- and high-resistance sites, shorts, and opens as well as ion implantation and metal patterning defects.

In this case study, the author describes the investigation of a defective DC-DC converter retrieved from an aircraft following the report of abnormal system behavior. Electrical testing, local probing, X-ray imaging, and cross-sectional analysis led to the discovery of cracks on several pins and in some of the solder material. The cracks were caused by different rates of thermal expansion and were remedied with the help of thermomechanical analysis, EBSD imaging, and phase map comparisons for thick and thin solder joints.