Search Results for mixed-signal ICs

This article discusses the challenges involved in testing analog and mixed-signal ICs and provides practical guidance and insights on how to deal with them.

Techniques used by failure analysts to provide proper stimuli to diagnose failures in mixed-signal ICs differ from routine digital IC tester stimuli. Mixed-signal parts not only require vector stimulus (i.e., set timing and frequency base), but also analog output sense signals, which are classified by differences in magnitude, frequency, and current. This article explains how a mixed-signal ASIC was analyzed using various signal stimuli.

This article presents an automation workflow for the development of analog and mixed-signal devices similar to the two-stage process used for the design and verification of logic ICs. The use of a co-simulation interface makes it possible to build and verify failure models.

This article explains how the addition of FIB tunable circuits in critical paths on ICs can alleviate some of the challenges encountered during the implementation of mixed-signal ASICs. It walks readers through the implementation of a particular digital ASIC, explaining where and how FIB tunable circuits were used to overcome difficulties, resolve problems, and realize a fully functional chip that met all system specifications on the first pass of the design.

Faster time-to-production of a new product is the common goal of design houses and foundries. This article demonstrates how foundries can contribute through post silicon validation, which allows design houses to focus on more complicated issues.

A wide range of electrical faults are revealed through thermal laser stimulation (TLS). In principle, an electrical parameter, typically current or voltage, is monitored for changes caused by the heating effects of the laser. Most test setups are designed to limit the activity of the device in order to minimize the signal-to-noise ratio, but in some cases, the fault’s electrical footprint can only be detected when the device is stimulated in a dynamic way. This article describes the setup and implementation of various dynamic TLS methods and presents example applications demonstrating the advantages and limitations of each approach.

Voltage contrast followed by electron beam induced current imaging is an effective approach for isolating IC failures. This article briefly reviews the physics of signal generation for both techniques and presents several examples illustrating how this powerful combination contributes to advanced defect localization.

Time-resolved emission (TRE) systems are used in many FA labs for internal timing analysis of digital ICs. In this article, the authors explain how they use TRE systems to diagnose analog circuit failures as well. The key to their success is the use of an asynchronous trigger on the emission detector, which eliminates measurement error due to nonlinear distortion. A case study of an analog amplifier failure caused by a polysilicon short demonstrates the effectiveness of their technique.

Scanning probe microscopy (SPM) refers to a suite of techniques that measure the interaction between a fine probe or tip and a sample in contact or close proximity. These interaction measurements allow the study of properties such as topology, magnetic and electric fields, capacitance, temperature, work function, and friction. The information obtained from SPM plays an important role in IC failure analysis.

At a Silicon Valley panel discussion on bringing new ICs to market, there was no mention by anyone onstage of a debug strategy, let alone its importance. This month’s guest columnist offers his insight on why that is and what should be done about it.

One of the pioneering developers of induced voltage alteration (IVA) measurement techniques assesses the current state of the technology, the impact of major advancements, and the potential for further improvements. The assessment pays particular attention to biasing approaches, phase-locked loop detection techniques, the effect of solid immersion lenses on spatial resolution, and the emergence of production-type sample preparation methods.

Off-state leakage currents account for roughly half of the total current is today’s ICs, and with each new generation of technology, the problem is getting worse. Failure analysts, however, see things differently. Light emission associated with leakage current is a rich source of information about the operation of ICs. In this article, the authors explain how they use this light to monitor logic states, measure temperatures, analyze cross-talk and power distribution noise, and diagnose broken scan chains. Light emission from off-state leakage current (LEOSLC) is shown to be especially useful for diagnosing faults that reside in scan clock trees, which are otherwise very difficult to detect.

The semiconductor industry has followed Moore’s law in the last four decades. However, transistor performance improvement will be limited, and designers will not see doubling of frequency every two years. The need for increased performance and further miniaturization has driven the development of advanced packaging solutions, such as fan-in wafer-level chip-scale packaging, fan-out wafer-level packaging, wire-bonded stacked dice, and package-on-package. These technologies are used in mass production and provide significant benefits in form factor but may not give the desired improvement in die-to-die bandwidth. Recently, 3-D integrated circuits (ICs) that employ vertical through-silicon vias (TSVs) for connecting each die have been proposed. It is an alternative solution to existing package-on-package and system-in-package processes. This column addresses some of the challenges in implementing new TSV techniques.

The 42nd International Symposium for Testing and Failure Analysis (ISTFA 2016) was held in Fort Worth, Texas, November 6-10, 2016. This article provides a summary of the keynote presentation, technical program, panel discussion, tutorials, and User’s Group meetings.

Dynamic laser stimulation is widely used in the PASS/FAIL mapping mode for soft defect localization. Recent improvements, including parametric mapping and multiple-parameter acquisition, significantly increase the amount of information that can be extracted from DLS measurements. This article explains where and how these new techniques are used and how they may be even further improved.

Researchers at Boston University have made significant improvements in the resolution that can be achieved with backside imaging techniques. In this article, they explain how they optimize lateral and longitudinal resolution of IR-based methods using aplanatic solid immersion lenses in combination with adaptive optics that correct for aberrations, interferometry to improve signal-to-noise ratios, vortex beams that overcome diffraction limitations, and image reconstruction techniques based on prior knowledge about the objects under investigation.

It seems that scaling of chip technology according to Moore’s Law will continue for digital functionalities (logic and memory); however, increasing system integration on chip and package levels, called “More than Moore,” has been observed in the past several years. This strong trend in the worldwide semiconductor industry enables more functionality, diversification, and higher value by creating smart microsystems. This article discusses the many challenges faced in FA of 3-D chips, where well-staffed and equipped FA labs are essential. Furthermore, FA is becoming an important strategic enabling factor for new products, not just another “cost factor.”

The Assembly Analytical Forum (AAF) is an organization under the auspices of the Sematech Quality Council. The AAF charter is to develop Packaging Analytical Roadmaps five to ten years into the future that are consistent with the International Technology Roadmap for semiconductors (ITRS). At ISTFA 2003, the AAF will convene with interested conference attendees to review, edit, and validate a white paper that will quantify critical gaps in the current suite of test, measurement, and characterization tools used in the semiconductor industry and provide recommendations on how to address them. The intent is to update the document biannually and review it in numerous industry venues to ensure its relevancy and utility. This article is somewhat of a preview to the Rev 0 AAF white paper.

A brief look at the roots of ISTFA, the International Symposium for Testing and Failure Analysis.

This article provides a high level overview of high speed analog circuits and associated failure analysis techniques. It discusses the failure modes and mechanisms of voltage reference circuits, high speed op amps, and digital-to-analog and analog-to-digital converters, the fundamental building blocks used to create high speed analog devices. It also explains how to deal with difficulties involving circuit node access, circuit loading, and performance.