Lightly doped source-drain diffusions are difficult if not impossible to delineate using wet chemical etching, but with a few process modifications and the use of edge shorting, a 20:1 HNO 3 /HF etch for 5 s at room temperature can reveal almost any junction profile in a CMOS device. The relatively simple process is outlined in this installment of Master FA Technique, which also includes a series of images showing how well the method works.

Nanoprobing of transistors and resistors is increasing in importance for both design debug and electrical fault isolation. It is thus necessary to understand the impact of scanning a resistor or transistor with an electron beam in order to draw valid conclusions from nanoprobe measurements. In this article, the authors show that exposing samples to electron beams with energies above 4 keV can change the value of diffusion resistors by as much as 30% and that changes can occur at even lower voltages in areas of the sample covered with less material. The article also sheds light on why the changes occur.

This article discusses some of the early uses of emission microscopy in semiconductor device failure analysis and the challenges that were overcome to make it the invaluable tool it is today. One of the impediments early on was a misconception that silicon cannot emit light when, in fact, it has several light emission mechanisms that have proven useful in electron microscopy. One such mechanism, avalanche luminescence, occurs in junctions during reverse breakdown and is useful for resolving low breakdown voltage and problems with ESD protection circuits. Other light emission mechanisms discussed in the article include forward bias emission, MOS transistor saturation, and dielectric luminescence, which is used to examine oxide test structures and detect oxide defects.

Electron beam induced current (EBIC) analysis is a versatile tool that can be used by anyone with access to a SEM. This article explains how failure analysts are using the EBIC mode in SEMs to detect junction and oxide defects, simplify junction delineation, and reveal subsurface damage through multiple layers of metallization.

This article explains how the addition of FIB tunable circuits in critical paths on ICs can alleviate some of the challenges encountered during the implementation of mixed-signal ASICs. It walks readers through the implementation of a particular digital ASIC, explaining where and how FIB tunable circuits were used to overcome difficulties, resolve problems, and realize a fully functional chip that met all system specifications on the first pass of the design.

Sandia National Laboratories manufactures 0.5 µm CMOS ICs using local oxidation of silicon (LOCOS) and shallow trench isolation (STI) technologies. A program based on burn-in and life tests is being used to qualify the process for military and space applications. Representative ICs from baseline wafer lots are assembled in ceramic packages and electrically tested before, during, and after burn-in and subsequent life tests. Two types of ICs are being used for this qualification, a 256K-bit SRAM and a microcontroller core. More than 600 ICs have passed qualification tests with very few failures, although recently, a group of SRAMs from a development wafer lot incorporating nonqualified processes had an usually high number of failures during their initial electrical test after packaging. This article describes the investigation that was conducted to determine the cause of these failures.

This article discusses the effect of hot carrier injection, bias temperature instability, and time-dependent dielectric breakdown on FinFET performance and reliability.