This article provides a qualitative overview of several new defect localization techniques, including charge-induced voltage alteration (CIVA), light-induced voltage alteration (LIVA), thermally-induced voltage alteration (TIVA), and Seebeck effect imaging (SEI). It explains how each method works in terms of the physics of signal generation and the types of images they produce. It also includes a summary highlighting the similarities and differences of each technique.

This article provides a high-level review of the tools and techniques used for backside analysis. It discusses the use of laser scanning and conventional microscopy, liquid and solid immersion lenses, photon emission microscopy (PEM), and laser-based fault isolation methods with emphasis on light-induced voltage alteration (LIVA). It explains how laser voltage probing is used for backside waveform acquisition and describes backside sample preparation and deprocessing techniques including parallel polishing and milling, laser chemical etching, and FIB circuit edit and modification.

One of the pioneering developers of induced voltage alteration (IVA) measurement techniques assesses the current state of the technology, the impact of major advancements, and the potential for further improvements. The assessment pays particular attention to biasing approaches, phase-locked loop detection techniques, the effect of solid immersion lenses on spatial resolution, and the emergence of production-type sample preparation methods.

The power of scanning optical microscopes (SOMs) lies in their ability to direct a small spot of light into an IC, producing photocarriers and heat in a localized area of the circuit. Photonic and thermal energy affect the I-V characteristics of the circuit in different ways, depending on the presence of defects and local material properties. This article explains how light beams interact with semiconductors and metals and how they influence the I-V characteristic of circuits and devices. It describes the basic physics of SOM measurements, provides examples of static and dynamic SOM techniques, and discusses emerging applications.

A team of semiconductor engineers recently developed a new fault localization method tailored for high-resistance faults. In this article, they discuss the basic principle of the technique and explain how they validated it for various test cases.

Laser stimulation is widely used to reveal defects in ICs through either heating or photonic effects. The standard approach is to use lasers with wavelengths above the bandgap wavelength of silicon to create localized heating and below it to generate photocurrent. In practice, most FAs use 1340 nm (IR) lasers for TIVA measurements and either 532 nm (visible) or 1064 nm (near IR) lasers for LIVA analysis. However, as this article demonstrates, visible and near IR lasers can also be used for TIVA analysis and, in some cases, may be preferrable based on signal strength and spatial resolution.

Thermally-induced voltage alteration (TIVA) is a laser-based method for localizing interconnect defects in ICs. Its main limitation is that the laser must heat the defect and change its resistance sufficiently to produce a measurable voltage alteration. Anything that interferes with laser absorption or alters defect heating makes TIVA less effective. This article presents the results of a study on the effects of local structures on TIVA imaging. The authors selected a polysilicon-metal test structure as the focal point of their study, which entailed experimental investigation along with modeling and simulation. It was found that the TIVA profiles on this structure are strongly influenced by local geometry, particularly the variation of interlevel silicon dioxide thickness and the placement of polysilicon lines with respect to aluminum lines. Understanding such relationships is essential for locating defects using TIVA techniques.

This article provides a high level overview of high speed analog circuits and associated failure analysis techniques. It discusses the failure modes and mechanisms of voltage reference circuits, high speed op amps, and digital-to-analog and analog-to-digital converters, the fundamental building blocks used to create high speed analog devices. It also explains how to deal with difficulties involving circuit node access, circuit loading, and performance.

Technologies relatively new to failure analysis, like time-correlated photon counting, electro-optical probing, antireflective (AR) coating, Schlieren microscopy, and superconducting quantum interference (SQUID) devices are being leveraged to create faster, more powerful tools to meet increasingly difficult challenges in failure analysis. This article reviews recent advances and research in fault isolation and circuit repair.

Recent developments in two relatively new failure analysis techniques, Seebeck effect imaging (SEI) and thermally-induced voltage alteration (TIVA), have greatly improved their defect detection sensitivity and image acquisition times for localizing open and shorted interconnections. This article presents several examples demonstrating the enhanced capabilities of these two methods.

Chip-level 3D integration, where chips are thinned, stacked, and vertically interconnected using TSVs and microbumps, brings as many challenges as it does improvements, particularly in the area of failure analysis. This article assesses the capabilities of various FA techniques in light of the challenges posed by 3D integration and identifies current shortcomings and future needs.

Several technology-focused User's Groups met at ISTFA 2014 to discuss current issues and advances in their areas of interest. This article summarizes key discussion points from the Contactless Fault Isolation User's Group, the Nanoprobing User's Group, the Sample Prep/3-D Package User's Group, and the FIB User's Group.

This article discusses the types of defects that occur in vertical cavity surface-emitting lasers (VCSELs) and the tools typically used to detect them and identify the cause. It describes the basic design and operation of VCSELs and explains that most failures are due to dislocations in the crystal structure of the materials from which the devices are made. Of the various methods used to analyze such defects, electroluminescence (EL) is by far the most powerful as demonstrated in several EL images included in the article. The article also discusses the use of EBIC analysis, FIB cross-sectioning, and thermally induced voltage alteration (TIVA).

The 40th International Symposium for Testing and Failure Analysis (ISTFA 2014) was held November 8 to 14, 2014, at the George R. Brown Convention Center in Houston, Texas. “Exploring the Many Facets of Failure Analysis,” the theme of ISTFA 2014, emphasized the diverse nature of semiconductor failure analysis in the 21st century. The technical sessions, keynotes, and tutorials at ISTFA 2014 covered a wide range of topics from fault isolation and sample prep to extreme environment failures and the birth of the digital signal processor.

Semiconductor trends, as embodied in the International Technology Roadmap for Semiconductors (ITRS), provide a guide for the challenges facing the failure analysis community. This process is a risk assessment of key features forecast for the impact of future technologies on failure analysis. The technical challenges fall primarily into two categories: failure site isolation and physical analysis. The failure site isolation challenges are largely driven by the device complexity and reduced accessibility of circuit nets. Additional challenges arise due to the increase in device operating speed and pin count. The challenges in physical analysis are driven primarily by smaller device feature sizes and by the host of new materials being introduced. In addition to the technical challenges, infrastructure changes are also likely to occur. The industry paths for addressing these challenges are discussed.

This column assesses the current state and outlook for superconducting device technology and its application in exascale computing.

Wafer-level failure analysis plays an important role in IC fabrication, both in process development and yield enhancement. This article outlines the general flow for wafer-level FA and explains how it differs for memory and logic products. It describes the tools and procedures used for failure mode verification, electrical analysis, fault localization, sample preparation, chemical analysis, and physical failure analysis. It also discusses the importance of implementing corrective actions and tracking the results.

Photon emission microscopy (PEM) has proven to be a powerful tool for fault isolation and has adapted well to ongoing changes in technology and emerging needs. In this tutorial, the authors describe the fundamentals of photon emission, the essential elements of a typical PEM system, and the procedures involved in diagnosing various types of failures. They also classify a wide range of photon-emitting defects and explain how PEM is used for backside analysis of flip-chip packaged devices and for timing diagnostics.

Scanning electron microscopes (SEMs) are the dominant tool for electronic device testing, failure analysis, and characterization. This status was not apparent, however, when the first commercial SEM, the Cambridge Stereoscan, appeared in 1963. A market survey by the manufacturer at that time predicted total sales of six to ten units worldwide. For the last four decades, SEMs have sold at an average rate of one unit every 24 hours, with two out of every three instruments destined for the semiconductor industry.

Sandia National Laboratories manufactures 0.5 µm CMOS ICs using local oxidation of silicon (LOCOS) and shallow trench isolation (STI) technologies. A program based on burn-in and life tests is being used to qualify the process for military and space applications. Representative ICs from baseline wafer lots are assembled in ceramic packages and electrically tested before, during, and after burn-in and subsequent life tests. Two types of ICs are being used for this qualification, a 256K-bit SRAM and a microcontroller core. More than 600 ICs have passed qualification tests with very few failures, although recently, a group of SRAMs from a development wafer lot incorporating nonqualified processes had an usually high number of failures during their initial electrical test after packaging. This article describes the investigation that was conducted to determine the cause of these failures.