Electron beam induced current (EBIC) analysis is a versatile tool that can be used by anyone with access to a SEM. This article explains how failure analysts are using the EBIC mode in SEMs to detect junction and oxide defects, simplify junction delineation, and reveal subsurface damage through multiple layers of metallization.

Lightly doped source-drain diffusions are difficult if not impossible to delineate using wet chemical etching, but with a few process modifications and the use of edge shorting, a 20:1 HNO 3 /HF etch for 5 s at room temperature can reveal almost any junction profile in a CMOS device. The relatively simple process is outlined in this installment of Master FA Technique, which also includes a series of images showing how well the method works.

Scanning capacitance spectroscopy (SCS) is a new way to use a scanning capacitance microscope (SCM) to delineate pn junctions in silicon devices. SCS produces two-dimensional pn junction maps with features as small as 10 nm. It can also estimate the pn junction depletion width and hence doping levels near the junction. This article explains how SCS and SCMs allow a whole new regime of doping-related phenomena to be explored in Si devices and ICs.

Off-axis electron holography is a TEM-based imaging technique that reveals dopant anomalies and junction profiles in semiconductor devices. This article explains how the method works and how it is being used to visualize transistor source-drain regions, diffusion-related defects, and other features of interest in TEM samples. It also discusses related challenges and compares off-axis electron holography with other profiling techniques, particularly junction staining.

Wafer-level failure analysis plays an important role in IC fabrication, both in process development and yield enhancement. This article outlines the general flow for wafer-level FA and explains how it differs for memory and logic products. It describes the tools and procedures used for failure mode verification, electrical analysis, fault localization, sample preparation, chemical analysis, and physical failure analysis. It also discusses the importance of implementing corrective actions and tracking the results.

Scanning capacitance microscopy (SCM) has proven to be an effective tool for investigating doping-related failure mechanism in ICs. The examples in this article show how the author used SCM to solve various problems including premature breakdown due to pattern misalignment, threshold voltage variations caused by poly gate doping anomalies, and source-drain leakage due to channeling effects.