Failure analysis is becoming increasingly difficult with the emergence of 3D integrated packages due to their complex layouts, diverse materials, shrinking dimensions, and tight fits. This article demonstrates several FA techniques, including high-frequency scanning acoustic microscopy, lock-in thermography, and FIB cross-sectioning in combination with plasma ion etching or laser ablation. Detailed case studies show how the various methods can be used to analyze bonding integrity between different materials, chip-to-chip interface structures, buried interconnect defects, and through-silicon vias at either the device or package level.

This article shows how 3D XRM can be applied to nondestructively detect non-optimized assembly processes that can influence local stresses and overall device reliability. This makes it useful for process development and failure analysis. When used along with AI training models, 3D XRM can achieve analysis of highly integrated packaging structures with reasonable throughput for process validation and error correction guidance.

This article provides a summary of the ISTFA 2012 Panel Discussion on the FA challenges associated with 3D integrated packages.

The second Electronics Resurgence Initiative (ERI 2.0), sponsored by the U.S. Defense Advanced Research Project Agency (DARPA) Microsystems Technology Office (MTO), is focused on driving next generation dual use microelectronics for national security and domestic needs. The initiative focuses on creating U.S. capability for three-dimensional heterogeneous integration (3DHI) manufacturing and pursuing focused research for the manufacture of complex 3D microsystems. This guest editorial describes the outcomes from a three-day summit (Seattle, Washington, August 2023) where the initiative was launched.

A detailed analysis based on FIB etching and SEM image capture was conducted on a flip-chip solder joint deep inside a tablet PC. 3D views reconstructed from SEM images show what appears to be a copper pillar with a solder cap connected to a copper trace on the substrate. The investigators believe the joint was formed by thermal compression bonding with a preapplied underfill. The analysis also revealed the presence of voids and intermetallic compounds along with signs of filler entrapment.

3-D silicon integration is reaching the point where it may be deployed. 3-D silicon integration is different from 3-D packaging in that 3-D packaging involves whole packaged chips, and each chip can still be tested individually throughout the manufacturing and assembly process, such as at wafer test, before and after packaging, and before and after integration into a complex chip assembly. Thus, methods used to test, debug, and verify multichip modules are generally extensible into the 3-D packaging space. For 3-D silicon integration using through-silicon vias, the issue is debug or test access to an individual die in the stack. This article reports on efforts by an IEEE P1838 Working Group to develop a per die standard.

This article provides an overview of a commercial 3D X-ray system, explaining how it acquires high-resolution images of submicron defects in large intact samples. It presents examples in which the system is used to reveal cracks in thin redistribution layers, voids in organic substrates, and variations in TSV metallization on 300-mm wafers. As the authors explain, each scan can be done in as little as a few minutes regardless of sample size, and the resulting images are clear of the beam hardening artifacts that often cause problems in failure analysis and reverse engineering.

The semiconductor industry has followed Moore’s law in the last four decades. However, transistor performance improvement will be limited, and designers will not see doubling of frequency every two years. The need for increased performance and further miniaturization has driven the development of advanced packaging solutions, such as fan-in wafer-level chip-scale packaging, fan-out wafer-level packaging, wire-bonded stacked dice, and package-on-package. These technologies are used in mass production and provide significant benefits in form factor but may not give the desired improvement in die-to-die bandwidth. Recently, 3-D integrated circuits (ICs) that employ vertical through-silicon vias (TSVs) for connecting each die have been proposed. It is an alternative solution to existing package-on-package and system-in-package processes. This column addresses some of the challenges in implementing new TSV techniques.

The semiconductor industry continues to scale microelectronics in accordance with Moore’s Law, as the minimum feature size on integrated circuits has decreased from 800 nm in 1993 to 90 nm in 2003 to 22 nm today. In addition, manufacturing advances include 3-D packaging, with multiple dice stacked in various configurations, and 3-D integrated circuits that use through-silicon vias or through-oxide vias to connect the various dice layers. The Intelligence Advanced Research Projects Activity (IARPA) Circuit Analysis Tools (CAT) program is developing tools and techniques to ensure that the U.S. government has capabilities for circuit analysis at future technology nodes, specifically at 22 nm and beyond, and for chips assembled using advanced packaging techniques. This column describes the CAT program activities and goals.

The inverted orientation of a flip-chip packaged die makes it vulnerable to optical attacks from the backside. This article discusses the nature of that vulnerability, assesses the threats posed by optical inspection tools and techniques, and provides insights on effective countermeasures.

The Package Innovation Roadmap Council (PIRC) was established as part of the Failure Analysis Technology Roadmap activity at the direction of the EDFAS Board. This column provides an overview of a technical paper by the PIRC that highlights recent innovations, technology gaps, and future development trends in package fault isolation and failure analysis. The paper focuses on three main categories: 1) Artificial intelligence (AI) applications, 2) Sample handling, and 3) FA tool robustness.

It seems that scaling of chip technology according to Moore’s Law will continue for digital functionalities (logic and memory); however, increasing system integration on chip and package levels, called “More than Moore,” has been observed in the past several years. This strong trend in the worldwide semiconductor industry enables more functionality, diversification, and higher value by creating smart microsystems. This article discusses the many challenges faced in FA of 3-D chips, where well-staffed and equipped FA labs are essential. Furthermore, FA is becoming an important strategic enabling factor for new products, not just another “cost factor.”

Interposers play an important role in 2.5D and 3D packages, routing power and communication signals between dies while maintaining electrical contact with I/O pins. This role and their relatively simple construction makes interposers a target for malicious attacks. In this article, the authors assess the vulnerabilities inherent in the fabrication of interposers and describe various types of optical attacks along with practical countermeasures.

This article describes a proposed novel metric to furnish chip designers with a prognostic tool for x-ray imaging in the pre-silicon stage. This metric is fashioned to provide designers with a concrete measure of how visible the fine-pitched features of their designs are under x-ray inspection. It utilizes a combination of x-ray image data collection, analysis, and simulations to evaluate different design elements.

This column explains that silicon interposers, considered an interim solution to full 3D integration, may turn out to be more than a stepping stone along the path toward 3D ICs.

Packaging integration continues to increase in complexity, driving more samples into FA labs for development support and analysis. For many of the jobs, there is also a need for larger removal volumes, compounding the demand for tool time and throughput. Focused ion beam (FIB) and dual-beam FIB/SEM systems are helping to relieve the pressure with their ability to create site-specific cross sections and to facilitate gate-level circuit rewire and debug. This article reviews the impact of packaging trends on failure analysis along with recent improvements in FIB technology. It also presents examples that illustrate how these new FIB techniques are being applied to solve emerging packaging challenges.

The complexity of sample preparation and deprocessing has risen exponentially with the emergence of 2.5-D and 3D packages. This article provides answers and insights on how to deal with the challenges of increasingly complex semiconductor packages. After identifying pressing issues and potential bottlenecks with state-of-the-art FA flows, the authors present two case studies demonstrating the capabilities of electro-optical terahertz pulse reflectometry (EOTPR), plasma FIB milling, and 3D X-ray imaging. The FA results confirm the potential of all three techniques and indicate that a fully nondestructive integration flow for 3D packages may be achievable with further development and optimization.

The Assembly Analytical Forum (AAF) is an organization under the auspices of the Sematech Quality Council. The AAF charter is to develop Packaging Analytical Roadmaps five to ten years into the future that are consistent with the International Technology Roadmap for semiconductors (ITRS). At ISTFA 2003, the AAF will convene with interested conference attendees to review, edit, and validate a white paper that will quantify critical gaps in the current suite of test, measurement, and characterization tools used in the semiconductor industry and provide recommendations on how to address them. The intent is to update the document biannually and review it in numerous industry venues to ensure its relevancy and utility. This article is somewhat of a preview to the Rev 0 AAF white paper.

The pace of development for 2.5-D packaging solutions appears to be accelerating as the timeline for the adoption of 3D through-silicon via (TSV) technology continues to slide. This column discusses the latest advancements in 2.5-D or interposer packaging technology and the growing number of applications.

This article addresses the considerations related to the development and introduction of new materials in response to the increasing performance demands of microelectronic devices, and how these new materials will affect characterization and failure analysis. The article is largely extracted from the “Deprocessing/Inspection White Paper” generated by the SEMATECH Product Analysis Forum (PAF), with updates from the PAF response to the International Technology Roadmap for Semiconductors.