Search Results for insulation damage

Integrated circuits are subjected to various forms of friction during fabrication and packaging, creating potential problems due to the buildup of charge. This article looks at the distinct characteristics of triboelectric charging damage on silicon-on-insulator devices at the wafer and package level. Telltale signs of this type of damage include spatial dependency, distinct TIVA-signal patterns, and bimodal static current distributions with significant changes after burn-in.

A large dc motor in a servo positioning system began behaving erratically whenever the rotor was in certain positions. This article describes the examinations and tests that were conducted to determine the root cause of failure, which turned out to be a shorted motor winding stemming form damage most likely caused by the tool used to pack the conductors into the core slot.

Coil failures can often be traced to an electrically open wire. In practice, coil wire breaks are the result of two or more failure mechanism acting together or in sequence. This article discusses the characteristics of different failure mechanisms and explains how to recognize them during analysis. Scanning electron micrographs of failed copper-wire ends presented in this article may be used as a guide in pinning down the cause of open-wire coil failures.

Flip chip mounted devices are difficult debug using conventional FIB tools because their internal circuitry is not easily accessible. New flip chip focused ion beam (FC FIB) systems overcome this limitation, however, making it possible to access circuits from the backside through the bulk silicon. In this article, the authors explain how they used the new system to gain access to signal lines for backside waveform acquisition. They also describe some of the procedures they developed to repair and modify flip chip circuits from the backside and prepare cross-section samples from the backside for failure analysis and characterization.

At the ISTFA ’99 event, the organizers arranged for the first time a panel discussion on failure analysis related purely to EOS/ESD issues. Each panelist presented their area of expertise followed by two hours of lively exchange with the attendees and among attendees. The panel discussed how to differentiate EOS and ESD failures. These failures are more critical with the industry move to submicron geometries and newer interconnect materials and other processing technologies, such as copper and flip-chip processing.

This article explains how oxide traps and mobile ions can lead to timing and function failures in ICs and provides insights and advice on how to identify and deal with potential problems.

The ability to discern the composition and placement of atoms in a sample makes TEM one of the most powerful characterization tools for microelectronic components. For many devices, however, the dynamics underlying normal operation do not displace atoms. Device function is, instead, mediated by electronic and thermal processes that have little effect on physical structure, necessitating additional tools to determine the causes of failure. In this article, the author presents results indicating that STEM EBIC, with the new SEEBIC mode, can provide electronic contrast that complements the physical-based contrast of STEM imaging. By identifying device features at higher risk of failure, the two methods may open a path to predictive failure analysis.

Copper wires are susceptible to damage during acid decapsulation and must be protected by stopping the process at the right moment. This article describes the development and evaluation of a method that uses polarization current measurements for end-of-etch detection and subsequent rinse.

A string of failures discovered during final testing after assembly led analysts on a long search for the cause, which turned out to be an unusual form of electrostatic discharge (ESD). Most ESD impacts on ICs occur by way of the pins. Nearly all ESD models, including the widely used human body model, charged-device model, and machine model, are based on this assumption. However, as this case study proves, passivated wafers and unpackaged dies are also susceptible to ESD damage. The authors explain that although this type of failure is difficult to diagnose, they were able to pinpoint the cause using lock-in microthermography and rule out mechanical-, FIB-, and laser-induced failures, which are similar in appearance.

Electromigration is a wearout mechanism that contributes significantly to IC failures. This article discusses the causes and effects of this often overlooked failure mode and presents practical guidelines to help analysts determine whether or not electromigration is the cause of a particular failure. It also discusses the differences between aluminum and copper electromigration.

This article explains why it has become necessary for equipment builders to analyze passive component failures and how the findings should be reported to manufacturers. It describes the general approach and steps involved in analyzing passive component failures and the methods and equipment used. It also explains how an actual failure involving a microwave switch was resolved.

This article provides an introduction to scanning ion microscopy, explaining how it overcomes one of the biggest limitations of SEMs, namely the tradeoff between spatial resolution and depth of field, while also providing significantly more surface detail, a wide range of novel and familiar contrast mechanisms, and the potential for new microanalytical techniques that combine nanometer spatial resolution and single monolayer sensitivity. In addition to describing the capabilities of scanning ion microscopes, the article also addresses the issue of sample charging and the potential for physical damage that can result from ion beam irradiation.

This article discusses sample preparation challenges that have impeded progress in producing bias-enabled TEM samples from electronic components, as well as strategies to mitigate these issues.

This article discusses the emergence of nanoelectronics and the effect it may have on semiconductor testing and failure analysis. It describes the different types of quantum effect and molecular electronic devices that have been produced, explaining how they are made, how they work, and the changes that may be required to manufacture and test these devices at scale.

This article presents the results of a study conducted at Sandia National Labs to assess the effect of electrostatic discharge on surface micromachined MEMS devices. This failure mode has largely been overlooked because ESD failure mechanisms often mimic the effects of stiction-adhesion. To measure the susceptibility of MEMS devices to ESD, Sandia engineers built and tested a silicon microengine and a torsional ratcheting microactuator. Test results indicate that the effects of ESD are highly dependent on device design, component stiffness, and geometry and that slight modifications can bring improvements.

This article discusses the basic principles of SEM-based cathodoluminescence (CL) spectroscopy and demonstrates its usefulness in process development, statistical process control, and failure analysis. The technologies where the benefits of CL spectroscopy are most evident are compound semiconductor optoelectronics and high electron mobility transistors as reflected in the application examples.

Chip-scale packages (CSPs) make efficient use of space on PCBs, but their small size, multilevel stacking arrangements, and complex interconnects present serious challenges when it comes to testing and failure analysis. This article describes some of the problems encountered when dealing with various types of CSPs and provides practical solutions based on the tools and techniques available in most FA labs. It discusses the causes and effects of package and die related failures and walks readers through the steps involved in decapsulating plastic FBGA packages using conventional etching, polishing, and milling techniques. It also includes a case study involving a failure caused by improper laser marking.

Scanning electron microscopes can be used to analyze almost anything that conducts electricity and is prone to failure, including relays, coils, inductors, capacitors, resistors, transistors, diodes, IGBTS, MOSFETS, and hybrid circuits. As the author of the article explains, SEMs are one of the most versatile tools for failure analysis if used to the full extent of their capabilities. Their operating modes include emissive imaging, backscattering, voltage contrast, EBIC or specimen current, and conductivity resistive mapping. The author describes each operating mode and presents examples of the various ways they can be used.

A new way to detect gate oxide defects has been developed. The method, as the article explains, is based on wet chemical etching and is particularly effective for devices with floating gates. Test samples with exposed poly-Si gates are placed in a KOH:H 2 O solution and a voltage is applied to the silicon substrate. At a certain voltage, normal gates begin to etch, while those shorted to the substrate through gate oxide defects develop an anodic oxide and thus remain unetched. This method has proven effective in assessing gate oxide integrity without direct observation of the oxide, which requires complicated deprocessing and a lot of time. It also reveals electrical characteristics of gate oxides that are difficult to identify by conventional physical analysis.

Dry tantalum electrolytic capacitors are widely used in electronic equipment because they have high capacitances at useful working voltages, low effective series resistances, relatively long life, and a small footprint. Tantalum capacitors have some limitations as well that, if not taken into account during circuit design, may produce catastrophic failures. The effect of one such limitation is highlighted in this detailed and well-illustrated case study.