This article presents a comprehensive study of physical inspection and attack methods, describing the approaches typically used by counterfeiters and adversaries as well as the risks and threats created. It also explains how physical inspection methods can serve as trust verification tools and provides practical guidelines for making hardware more secure.

Integrated circuits embedded in everyday devices face an increased risk of tampering and intrusion. In this article, the authors explain how reverse engineering techniques, including automated image analysis, can be employed to provide trust and assurance when dealing with commercial off-the-shelf chips.

This article proposes a design for a real-time Trojan detection system and explores possible solutions to the challenge of large-scale SEM image acquisition. One such solution, a deep-learning approach that generates synthetic micrographs from layout images, shows significant promise. Learning-based approaches are also used to both synthesize and classify cells. The classification outcome is matched with the design exchange format file entry to ensure the purity of the underlying IC.

Traditional post-fabrication testing can reliably verify whether or not an IC is working correctly, but it cannot tell the difference between an authentic and counterfeit chip or recognize design changes made with malicious intent. This article presents an IC decomposition workflow, based on FA tools and techniques, that provides a quantifiable level of assurance for components in a zero trust environment.

Further development of SEM-based feature extraction tools for design validation and failure analysis is contingent on reliable sample preparation methods. This article describes how a delayering framework for 130 nm technology was adapted and used on a 45 nm SPI module consisting of 11 metal layers, 10 via layers, two layers of polysilicon, and an active silicon layer. It explains how different polishing and etching methods are used to expose each layer with sufficient contrast for SEM imaging and subsequent feature extraction. By combining polygon sets representing each layer, the full design of the device was reconstructed as shown in one of the images.

Interposers play an important role in 2.5D and 3D packages, routing power and communication signals between dies while maintaining electrical contact with I/O pins. This role and their relatively simple construction makes interposers a target for malicious attacks. In this article, the authors assess the vulnerabilities inherent in the fabrication of interposers and describe various types of optical attacks along with practical countermeasures.

The second phase of the IARPA Circuit Analysis Tools (CAT) program, which ended in June 2015, focused on the development of prototype tools to demonstrate scalability to the 10 nm node. Our guest columnist, IARPA Program Manager, Carl E. McCants, provides a summary of what the participating teams accomplished.

The semiconductor industry continues to scale microelectronics in accordance with Moore’s Law, as the minimum feature size on integrated circuits has decreased from 800 nm in 1993 to 90 nm in 2003 to 22 nm today. In addition, manufacturing advances include 3-D packaging, with multiple dice stacked in various configurations, and 3-D integrated circuits that use through-silicon vias or through-oxide vias to connect the various dice layers. The Intelligence Advanced Research Projects Activity (IARPA) Circuit Analysis Tools (CAT) program is developing tools and techniques to ensure that the U.S. government has capabilities for circuit analysis at future technology nodes, specifically at 22 nm and beyond, and for chips assembled using advanced packaging techniques. This column describes the CAT program activities and goals.

This article describes a proposed novel metric to furnish chip designers with a prognostic tool for x-ray imaging in the pre-silicon stage. This metric is fashioned to provide designers with a concrete measure of how visible the fine-pitched features of their designs are under x-ray inspection. It utilizes a combination of x-ray image data collection, analysis, and simulations to evaluate different design elements.

This article describes a novel method for improving image resolution achieved using time-resolved photon emission techniques. Instead of directly generating images from photon counting, all detected photons are displayed as a point cloud in 3D space and a new higher-resolution image is generated based on probability density functions associated with photon distributions. Unsupervised learning algorithms identify photon distribution patterns as well as fainter emission sources.

The inverted orientation of a flip-chip packaged die makes it vulnerable to optical attacks from the backside. This article discusses the nature of that vulnerability, assesses the threats posed by optical inspection tools and techniques, and provides insights on effective countermeasures.

This article describes a hardware metering fingerprint technique, called the memometer, that addresses supply chain integrity issues with field-programmable gate arrays (FPGAs). The memometer is a physically unclonable function (PUF) based on cross-coupled lookup tables that overcomes manufacturing memory power-on preset. The fingerprints are not only unique, but also reliable with average hamming distances close to the ideal values of 50% (interchip) and 0% (intrachip). Instead of having one fingerprint per device, the memometer makes provision for hundreds with the potential for more.

Several technology-focused User's Groups met at ISTFA 2014 to discuss current issues and advances in their areas of interest. This article summarizes key discussion points from the Contactless Fault Isolation User's Group, the Nanoprobing User's Group, the Sample Prep/3-D Package User's Group, and the FIB User's Group.

This article discusses the advantages of SEM-based nanoprobing and the various ways it can be used to locate defects associated with IC failures. It describes the basic measurement physics of electron beam induced current, absorbed electron, and voltage distribution contrast imaging and presents examples showing how the different methods are used to isolate low- and high-resistance sites, shorts, and opens as well as ion implantation and metal patterning defects.

This article describes how physical attacks can be launched on different types of nonvolatile memory (NVM) cells using failure analysis tools. It explains how the bit information stored inside these devices is susceptible to read-out and fault injection attacks and defines vulnerability parameters to help quantify risks associated with different modalities of attack. It also presents an in-depth security analysis of emerging NVM technologies and discusses potential countermeasures.

Deprocessing of ICs is often the final step for defect validation in FA cases with limited fault-isolation information. This article presents a workflow for deprocessing ICs from the backside using automated thinning and large-area plasma FIB delayering. Advantages to this approach include a reduction in manual planarization and depackaging and a higher degree of precision and repeatability.

Circuit boards are vulnerable to a wide range of ill-intentioned modifications done to gain access to information or malevolently influence control. This article describes the various ways attacks on circuit board can occur and presents examples showing how such attacks might look. It also provides general guidelines for protecting circuit-board design integrity.

This article explains how the failure of a high-voltage capacitor led to the discovery of an unusual defect. Testing showed that the capacitor shorted due to silver migration, which investigators believe was facilitated by voids in the dielectric that had been present from the time of manufacture. Through some combination of time, electric potential, trapped humidity, and elevated operating temperature, plate material migrated into the voids, creating a short path that led to the failure. Using acoustic images as a guide, the failed capacitor was cross-sectioned, allowing investigators to examine the voids more closely and thereby confirm their theory.

The high energy-resolving power of superconducting x-ray detectors reduces unwanted x-ray backgrounds, uses x-ray photons efficiently, and allows for discrimination among multiple chemical elements in a sample. This article discusses the challenges of analyzing the internal structure and composition of integrated circuits, and how 3D imaging can benefit manufacturers and researchers. It covers the development of superconducting x-ray sensors, their advantages over traditional sensors, potential applications, and focus areas for future work to develop this technology.

This article describes a form of lock-in thermography that achieves 3D localization of thermally active defects in stacked die packages. In this approach, phase shifts associated with thermal propagation delay are analyzed as a function of frequency. This allows for a precise localization of defects in all three spatial dimensions and can serve as a guide for subsequent high-resolution physical analyses.