Search Results for gate drive circuit

This article discusses the causes and effects of parasitic ringing in the gate drive circuit of dc-to-dc converters. It also presents experimental results validating a possible solution.

This columnn explores the idea that insights into the root cause of increasingly complex failures may be hidden in unanswered questions from past analyses, indicating that there might be more value in previous files than once thought.

Packaging integration continues to increase in complexity, driving more samples into FA labs for development support and analysis. For many of the jobs, there is also a need for larger removal volumes, compounding the demand for tool time and throughput. Focused ion beam (FIB) and dual-beam FIB/SEM systems are helping to relieve the pressure with their ability to create site-specific cross sections and to facilitate gate-level circuit rewire and debug. This article reviews the impact of packaging trends on failure analysis along with recent improvements in FIB technology. It also presents examples that illustrate how these new FIB techniques are being applied to solve emerging packaging challenges.

This article examines the phenomenon of time-dependent dielectric breakdown (TDDB) in ultrathin gate oxide films and explains why it is no longer considered a catastrophic failure in MOSFET-containing ICs.

Designing circuit edits at the contact level offers tremendous advantages in reliability and yield success over similar edits designed in the metal stack. To that end, a full-thickness backside circuit edit strategy has been developed that eliminates part thinning and promotes the implementation of all edits at the contact level to avoid milling into the metal layers. This article describes the FIB-based circuit edit process and presents several case studies demonstrating its use on 65 nm technology devices.

Picosecond imaging circuit analysis (PICA) is an advanced diagnostic technique that measures device switching activity on CMOS ICs through the backside of the die. Due to its relatively large field of view, it can quickly locate defects among large numbers of candidates. In this case study, the authors explain how they used PICA to identify a particular I/O circuit defect on the IBM System/390 G5 microprocessor. They also explain how they verified the diagnostic result using circuit simulations.

Dealing with timing failures in nanometer-scale ICs requires a deeper understanding of critical timing paths, noise mechanisms, process variability, timing rules, and the statistical interaction of random parameter values and distributions. This article examines the factors that affect nanometer timing at both the component and system level. It reviews the timing properties of nanoscale logic gates, latches, edge-triggered flip-flops, clocks and their interconnects, resistive vias, and pipeline structures. It also discusses the challenges involved in determining critical timing paths and the underlying causes of nanometer timing failures.

Time-resolved emission (TRE) systems are used in many FA labs for internal timing analysis of digital ICs. In this article, the authors explain how they use TRE systems to diagnose analog circuit failures as well. The key to their success is the use of an asynchronous trigger on the emission detector, which eliminates measurement error due to nonlinear distortion. A case study of an analog amplifier failure caused by a polysilicon short demonstrates the effectiveness of their technique.

Off-state leakage currents account for roughly half of the total current is today’s ICs, and with each new generation of technology, the problem is getting worse. Failure analysts, however, see things differently. Light emission associated with leakage current is a rich source of information about the operation of ICs. In this article, the authors explain how they use this light to monitor logic states, measure temperatures, analyze cross-talk and power distribution noise, and diagnose broken scan chains. Light emission from off-state leakage current (LEOSLC) is shown to be especially useful for diagnosing faults that reside in scan clock trees, which are otherwise very difficult to detect.

This article discusses the causes and effects of stuck-open faults (SOFs) in nanometer CMOS ICs. It addresses detection and localization challenges and explains how resistive contacts and vias and the use of damascene-copper processes contribute to the problem. It also discusses layout techniques that reduce the likelihood of SOF failures.

ICs designed for portable devices often make use of reverse-body bias (RBB) modes to limit leakage currents. The added complexity of RBB support circuitry presents a challenge during IC characterization and debug. This article discusses the nature of the problem and explains how to identify irregularities in circuits operating in the body-biased condition using standard debug tools with simple modifications. It describes some of the bugs discovered in an actual examination and explains how they were diagnosed by analyzing I-V curve traces and infrared emission microscopy (IREM) images.

This article discusses the effect of hot carrier injection, bias temperature instability, and time-dependent dielectric breakdown on FinFET performance and reliability.

A new product-like test chip developed by engineers at Carnegie Mellon University overcomes the current limitations in conventional test chip design. This article discusses the advantages of the new chip, called the CM-LCV, and presents experimental results showing how it achieves fault coverages comparable to or better than benchmarking designs.

Semiconductor trends, as embodied in the International Technology Roadmap for Semiconductors (ITRS), provide a guide for the challenges facing the failure analysis community. This process is a risk assessment of key features forecast for the impact of future technologies on failure analysis. The technical challenges fall primarily into two categories: failure site isolation and physical analysis. The failure site isolation challenges are largely driven by the device complexity and reduced accessibility of circuit nets. Additional challenges arise due to the increase in device operating speed and pin count. The challenges in physical analysis are driven primarily by smaller device feature sizes and by the host of new materials being introduced. In addition to the technical challenges, infrastructure changes are also likely to occur. The industry paths for addressing these challenges are discussed.

This column discusses the effect of changes in the U.S. patent process and explains how they benefit failure analysts. He also relates one of his own experiences with filing for a patent based on an observation he and a colleague made in a semiconductor FA lab.

Parametric failures are of two general types. One type is due to defects that affect circuit parameters. The other type, which occurs in defect-free parts, is the result of interdie parameter statistical variation. IC failures can be caused by variations in any number of parameters including L eff , W eff , I Dsat , V t , contact resistance, effective gate oxide thickness, source and drain resistance, interconnect sheet resistance, and intrametal spacing affecting cross-talk, ground bounce noise, and IR voltage drops. These failures often influence the maximum operating frequency of the IC and are seldom detected by simple stuck-at fault, delay fault, functional, or I DDQ tests. This article discusses the origin, classification, and detection of a wide range of parametric failures.

This article explains how laser voltage probing (LVP) can be used to analyze combinational logic circuits. The authors describe how the technique is aided by the development and use of a waveform library and a corresponding truth table. They also present a case study in which the new technique is used to isolate faults in a combinational logic circuit consisting of multiple gates.

The Electronic Device Failure Analysis Society established the Die-Level Post-Isolation Domain Council to provide an overview of the upcoming challenges in this area and guide technique developments for next-generation analytical tools. This column summarizes the findings of the council in the areas of sample preparation, microscopy, nanoprobing, circuit editing, and scanning probe microscopy. It is a preview of the full roadmap document, which is in preparation to be released to the EDFAS community.

A noninvasive thermal imaging approach based on the thermoreflectance principle is proposed for analyzing advanced semiconductor devices. Several examples illustrate the value of this approach in detecting thermal anomalies and defects missed by other techniques.

Soft electrical failures caused by monograin defects can have a significant impact on yield in technology nodes below 40 nm. Moreover, the failures are hard to identify and the defects give very few signatures during localization testing. In this article, the authors explain how they used nanobeam diffraction with automated crystal orientation and phase mapping to pinpoint a single grain orientation causing the problem and, as a result, are now able to recognize the symptoms of this type of failure, observe the defect, and limit the impact on electrical timing margins through both design and process corrections.