Thin film anomalies cause many device failures but they are often difficult to see. In this article, the authors explain how they found and identified an 8 to 10 nm film of tantalum causing pin shorts in a majority of ASIC modules from a particular lot. Initial attempts to delayer some of the failed modules resulted in the loss of the failure signal. It was then decided to use a focused ion beam to selectively mill through the interlayer dielectric. During milling, a secondary electron image revealed anomalous material between the fingers of a power transistor, which was subsequently identified as tantalum. Such defects, as the authors explain, are common in damascene processes when materials are not properly removed during etching.

Atomic force microscopy has been a consistent factor in the advancements of the past decade in IC nanoprobing and failure analysis. Over that time, many new atomic force measurement techniques have been adopted by the IC analysis community, including scanning conductance, scanning capacitance, pulsed current-voltage, and capacitance-voltage spectroscopy. More recently, two new techniques have emerged: diamond probe milling and electrostatic force microscopy (EFM). As the authors of the article explain, diamond probe milling using an atomic force microscope is a promising new method for in situ, localized, precision delayering of ICs, while active EFM is a nondestructive alternative to EBAC microscopy for localization of opens in IC analysis.

Plasma focused ion beam (PFIB) systems can generate ion beams with much higher current and are therefore able to remove larger volumes of material at much faster rates while still maintaining precise control of the beam and its milling action. This article explains how the improved performance of PFIB is leading to new applications in delayering, deprocessing, and site-specific failure analysis.

Packaging integration continues to increase in complexity, driving more samples into FA labs for development support and analysis. For many of the jobs, there is also a need for larger removal volumes, compounding the demand for tool time and throughput. Focused ion beam (FIB) and dual-beam FIB/SEM systems are helping to relieve the pressure with their ability to create site-specific cross sections and to facilitate gate-level circuit rewire and debug. This article reviews the impact of packaging trends on failure analysis along with recent improvements in FIB technology. It also presents examples that illustrate how these new FIB techniques are being applied to solve emerging packaging challenges.

The sixth FIB-SEM workshop was held March 1, 2013, in Cambridge, Mass. This article provides a summary of the event along with highlights from the 18 paper presentations.

This article discusses sample preparation challenges that have impeded progress in producing bias-enabled TEM samples from electronic components, as well as strategies to mitigate these issues.

Ex-situ lift out (EXLO) techniques rely on van der Waals forces to transfer FIB milled specimens to various types of carriers using a glass probe micromanipulator. This article describes some of the latest EXLO techniques for site specific scanning transmission electron microscopy, including the use slotted half-grids and vacuum-assisted lift out for plan-view analysis.

TEM specimens prepared using a Ga FIB are susceptible to artifacts, such as surface amorphization and ion-implanted layers, that can be problematic in advanced technology nodes, particularly for FinFETs. As this article shows, however, post-FIB cleaning via concentrated argon ion milling makes for a fast and effective specimen preparation process for FinFET devices controlled to a thickness of less than 20 nm. Although the results presented here are based on 14 nm node FinFETs, the method is also applicable to the 10 and 7 nm FinFET technologies currently in production.

This is the story of how the mainstream Omniprobe FIB lift-out solution was invented and delivered to the market.

Deprocessing of ICs is often the final step for defect validation in FA cases with limited fault-isolation information. This article presents a workflow for deprocessing ICs from the backside using automated thinning and large-area plasma FIB delayering. Advantages to this approach include a reduction in manual planarization and depackaging and a higher degree of precision and repeatability.

Designing circuit edits at the contact level offers tremendous advantages in reliability and yield success over similar edits designed in the metal stack. To that end, a full-thickness backside circuit edit strategy has been developed that eliminates part thinning and promotes the implementation of all edits at the contact level to avoid milling into the metal layers. This article describes the FIB-based circuit edit process and presents several case studies demonstrating its use on 65 nm technology devices.

The presence of copper layers separated by low-k dielectrics in today’s ICs is a major problem for circuit edit engineers. This article explains why and presents a solution that addresses the challenges CE engineers face. According to the authors, the difficulties are primarily due to the interaction of the ion beam with variations in copper grain orientation, the effects of halogen corrosion, and the presence of CuF. As a result, copper milling tends to be uneven and edit times tend to be quite long. The solution presented is based on a chemically-assisted milling and etching process that quickly and uniformly removes copper and dielectric layers while maintaining planarity.

Scanning capacitance microscopy (SCM) has proven to be an effective tool for investigating doping-related failure mechanism in ICs. The examples in this article show how the author used SCM to solve various problems including premature breakdown due to pattern misalignment, threshold voltage variations caused by poly gate doping anomalies, and source-drain leakage due to channeling effects.

High-frequency devices such as monolithic microwave ICs (MMICs) are used in telecommunication devices as well as in satellites for earth imaging and radar applications. This article discusses the use of focused ion beam (FIB) cross sectioning and sample decoration techniques for analyzing MMICs and III-V materials.

FIB circuit edit tools and techniques have thus far kept pace with the evolution of interconnect materials in ICs and downward scaling of device dimensions. This article assesses the coming challenges for FIB circuit edit technology and the changes that will be necessary to keep FIB-based etching, milling, and deposition viable in the future.

Flip chip mounted devices are difficult debug using conventional FIB tools because their internal circuitry is not easily accessible. New flip chip focused ion beam (FC FIB) systems overcome this limitation, however, making it possible to access circuits from the backside through the bulk silicon. In this article, the authors explain how they used the new system to gain access to signal lines for backside waveform acquisition. They also describe some of the procedures they developed to repair and modify flip chip circuits from the backside and prepare cross-section samples from the backside for failure analysis and characterization.

This article addresses the considerations related to the development and introduction of new materials in response to the increasing performance demands of microelectronic devices, and how these new materials will affect characterization and failure analysis. The article is largely extracted from the “Deprocessing/Inspection White Paper” generated by the SEMATECH Product Analysis Forum (PAF), with updates from the PAF response to the International Technology Roadmap for Semiconductors.

This article discusses recent improvements in FIB circuit edit as well as general uses and optimization techniques.

This article provides a summary of each of the four User’s Group meetings that took place at ISTFA 2011. The summaries cover key participants, presentation topics, and discussion highlights from each of the following groups: Group 1, Focused Ion Beam; Group 2, 3D Packaging and Failure Analysis; Group 3, Finding the Invisible Defect; and Group 4, Nanoprobing and Electrical Characterization.

Recent developments in automated image acquisition and metrology using transmission electron microscopy (TEM) and scanning transmission electron microscopy (STEM) have significantly improved the speed, precision, and usability of these techniques for controlling advanced semiconductor device manufacturing processes. As device dimensions have continued to shrink, these techniques may be needed to replace scanning electron microscopy (SEM) for the smallest critical dimension (CD) measurements. This article describes the use of automated S/TEM in a high-throughput CD-metrology workflow to support process development and control and explains how automated sample-preparation, data-acquisition, and metrology tools increase both throughput and data quality.