Scanning microwave impedance microscopy (sMIM) is a relatively new method for making electrical measurements on test samples in AFMs. This article presents examples in which sMIM technology is used to measure dielectric coefficients, doping concentrations, and nanoscale C-V curves for different semiconductor and dielectric materials. It also explains how measured results compare with theoretical models, confirming the validity of each approach.

Mechanical bending strength measurements, part of a quality screening process for ceramic substrate package designs, revealed a significant difference between two substrates that could not be attributed to constituent materials or structural thickness effects. Structural analysis was performed to generate a hypothesis that the metal vias were not structurally adhered to the ceramic holes and thus caused stress concentrations that reduced the bending strength of the substrates. In this detailed case study, the authors explain how they proved their hypothesis using FEA to calculate stress concentration factors, optical microscopy to examine fracture surfaces, and electron spectroscopy to determine chemical compositions. The successful outcome attests to the value of strength criteria as an investigative tool for the assessment of electronic package substrate quality.

A numerical investigation of the probabilistic approach in estimating the reliability of wire bonding is presented along with a reliability based design optimization methodology for microelectronic devices structures.

This column explains how simulation tools and materials life data can provide a new level of productivity for engineers involved in forensic analysis of MEMS devices.

It seems that scaling of chip technology according to Moore’s Law will continue for digital functionalities (logic and memory); however, increasing system integration on chip and package levels, called “More than Moore,” has been observed in the past several years. This strong trend in the worldwide semiconductor industry enables more functionality, diversification, and higher value by creating smart microsystems. This article discusses the many challenges faced in FA of 3-D chips, where well-staffed and equipped FA labs are essential. Furthermore, FA is becoming an important strategic enabling factor for new products, not just another “cost factor.”

Thermally-induced voltage alteration (TIVA) is a laser-based method for localizing interconnect defects in ICs. Its main limitation is that the laser must heat the defect and change its resistance sufficiently to produce a measurable voltage alteration. Anything that interferes with laser absorption or alters defect heating makes TIVA less effective. This article presents the results of a study on the effects of local structures on TIVA imaging. The authors selected a polysilicon-metal test structure as the focal point of their study, which entailed experimental investigation along with modeling and simulation. It was found that the TIVA profiles on this structure are strongly influenced by local geometry, particularly the variation of interlevel silicon dioxide thickness and the placement of polysilicon lines with respect to aluminum lines. Understanding such relationships is essential for locating defects using TIVA techniques.

Although much traditional FA depends on physical observation to localize failures, electrical techniques are also important, particularly with advances in design for testability (DFT) on modern ICs. DFT structures combined with automated test equipment and algorithmic fault diagnosis facilitate a test-based fault localization (TBFL) approach to identify defect locations on ICs based on scan test patterns. This article and a companion piece in the November 2001 issue of EDFA provide an overview these methods and show how they can reduce the number of potential defect sites on a chip and, in some cases, identify defects that would be missed by other techniques.

This article presents the principles of scanning thermal microscopy (SThM) instruments and their potential uses for the local thermal analysis of passive and active electronic components and devices. Three examples are given that demonstrate the SThM’s ability to perform thermal analysis on a microscopic scale. The results suggest that SThM could be used as a powerful tool for analyzing printed circuit boards and electronic devices with high spatial resolution, during the development cycle, failure analysis during and after manufacture, and during operation.

This article provides a brief introduction to through-silicon via technology, a system-level architecture in which multiple layers of planar devices are stacked with interconnects running in the vertical as well as lateral direction. Some of the different fabrication processes in use are discussed along with related challenges.

Scanning microwave impedance microscopy (sMIM) is an electrical measurement technique that can be used to determine dopant profiles in semiconductor devices. This article describes the basic setup and implementation of the method and demonstrates its use in the cross-sectional analysis of NMOS power transistors.

Electronic components and assemblies are subjected to temperature variations at every stage of life, resulting in the buildup of internal stress. This article explains how such stress contributes to failures and introduces a measurement technique that allows users to visualize stress distributions and assess their effects on lifetime and reliability. Application examples illustrating the capabilities of the new topography and deformation measurement approach are also presented.

The influence of electric current flow and electrically induced Joule heat on thermal stress for weld joint cracks at both interfaces is still not fully comprehended. This article investigates the effect of subjecting the ball grid array package to a cyclic current input. Current density, Joule effect, and temperature curves are examined.

Transmission electron microscopy (TEM) plays an important role semiconductor process development, defect identification, yield improvement, and root-cause failure analysis. At the same time, however, certain artifacts of specimen preparation and imaging present barriers for linear scaling of TEM techniques. This article assesses these challenges and explains how electron tomography is being used to overcome them.

The causes of failure in flip-chip packaged devices are often found at the interface between the die and package. Exposing the site of interest usually entails some form of mechanical cross-sectioning with the sample embedded in an epoxy puck. This article brings attention to some of the drawbacks with the current approach and presents a solution in the form of a redesigned puck. As test results show, the new puck significantly reduces polishing time, and when cast with a conductive epoxy, minimizes charging artifacts and image distortion during SEM analysis. It also facilitates easy sample removal for subsequent analysis.

Technologies relatively new to failure analysis, like time-correlated photon counting, electro-optical probing, antireflective (AR) coating, Schlieren microscopy, and superconducting quantum interference (SQUID) devices are being leveraged to create faster, more powerful tools to meet increasingly difficult challenges in failure analysis. This article reviews recent advances and research in fault isolation and circuit repair.

This article provides a summary of each of the four User’s Group meetings that took place at ISTFA 2011. The summaries cover key participants, presentation topics, and discussion highlights from each of the following groups: Group 1, Focused Ion Beam; Group 2, 3D Packaging and Failure Analysis; Group 3, Finding the Invisible Defect; and Group 4, Nanoprobing and Electrical Characterization.

This article presents a comprehensive study of physical inspection and attack methods, describing the approaches typically used by counterfeiters and adversaries as well as the risks and threats created. It also explains how physical inspection methods can serve as trust verification tools and provides practical guidelines for making hardware more secure.