This article discusses the advantages of SEM-based nanoprobing and the various ways it can be used to locate defects associated with IC failures. It describes the basic measurement physics of electron beam induced current, absorbed electron, and voltage distribution contrast imaging and presents examples showing how the different methods are used to isolate low- and high-resistance sites, shorts, and opens as well as ion implantation and metal patterning defects.

The best spatial resolution that can be achieved with far-field optical fault localization techniques is around 20 times larger than the critical defect size at the 45 nm technology node. There is also a limit on the laser power that can be safely used on 45 nm devices, which further compromises fault localization precision. In this article, the authors explain how they overcome these limitations using pulsed laser-induced imaging techniques and a refractive solid immersion lens. Two case studies show how the combination of pulsed-laser scanning optical microscopy and a solid immersion lens improves localization precision and detection sensitivity.

Although much traditional FA depends on physical observation to localize failures, electrical techniques are also important, particularly with advances in design for testability (DFT) on modern ICs. DFT structures combined with automated test equipment and algorithmic fault diagnosis facilitate a test-based fault localization (TBFL) approach to identify defect locations on ICs based on scan test patterns. This article and a companion piece in the November 2001 issue of EDFA provide an overview these methods and show how they can reduce the number of potential defect sites on a chip and, in some cases, identify defects that would be missed by other techniques.

A team of semiconductor engineers recently developed a new fault localization method tailored for high-resistance faults. In this article, they discuss the basic principle of the technique and explain how they validated it for various test cases.

This article presents a nanoprobing method that uses high-speed pulses to characterize in-die SRAM bit cells. The authors describe the basic setup of the test system and demonstrate its use on a six-transistor bit cell failure. The method reduces fault localization time and decreases the possibility of deprocessing past the fail because testing is done at metallization layer 1. The bit’s reaction is captured in the form of analog current measurements, resulting in a unique signature of the failure.

Wafer-level failure analysis plays an important role in IC fabrication, both in process development and yield enhancement. This article outlines the general flow for wafer-level FA and explains how it differs for memory and logic products. It describes the tools and procedures used for failure mode verification, electrical analysis, fault localization, sample preparation, chemical analysis, and physical failure analysis. It also discusses the importance of implementing corrective actions and tracking the results.

In most cases, microelectronic failure analysis is rooted in the observation of voltage, either as logic levels or as time-based waveforms. This is due largely to the ease of making such measurements. As a result, current measurement is often overlooked. This article discusses aspects of current measurement that can be used during fault localization, often providing information that cannot be obtained by other means.

The use of a pulsed laser with a lock-in amplifier has been shown to increase the detection sensitivity of scanning optical microscopes by a factor of ten. In this article, the authors explain how they implement laser pulsing without a lock-in amplifier through software control. The detection sensitivity of their method, which is based on a digital signal integration algorithm, has been shown to be comparable to that achieved with a lock-in amplifier. Several case studies illustrate the effectiveness of the technique for locating various types of defects.

This article discusses the types of defects that occur in vertical cavity surface-emitting lasers (VCSELs) and the tools typically used to detect them and identify the cause. It describes the basic design and operation of VCSELs and explains that most failures are due to dislocations in the crystal structure of the materials from which the devices are made. Of the various methods used to analyze such defects, electroluminescence (EL) is by far the most powerful as demonstrated in several EL images included in the article. The article also discusses the use of EBIC analysis, FIB cross-sectioning, and thermally induced voltage alteration (TIVA).

Selecting a fault isolation technique for a particular type of SRAM logic failure requires an understanding of available methods. In this article, the authors review common fault isolation techniques and present several case studies, explaining how they determined which technique to use.

One of the pioneering developers of induced voltage alteration (IVA) measurement techniques assesses the current state of the technology, the impact of major advancements, and the potential for further improvements. The assessment pays particular attention to biasing approaches, phase-locked loop detection techniques, the effect of solid immersion lenses on spatial resolution, and the emergence of production-type sample preparation methods.

Electro optical terahertz pulse reflectometry (EOTPR) is a nondestructive fault isolation technique that is well suited for today’s ICs. This article provides examples of how EOTPR is being used to investigate 2.5D and 3D packages, wafer level fanout packages, and MEMS devices. It also discusses recent advancements in EOTPR systems and software.

A wide range of electrical faults are revealed through thermal laser stimulation (TLS). In principle, an electrical parameter, typically current or voltage, is monitored for changes caused by the heating effects of the laser. Most test setups are designed to limit the activity of the device in order to minimize the signal-to-noise ratio, but in some cases, the fault’s electrical footprint can only be detected when the device is stimulated in a dynamic way. This article describes the setup and implementation of various dynamic TLS methods and presents example applications demonstrating the advantages and limitations of each approach.

An optically polished silicon surface with controlled sample thickness is the key to successful backside imaging. Achieving that manually can be very difficult in cases where ICs are encapsulated in packaging materials. This article describes the challenges involved with traditional (manual) backside silicon sample preparation techniques and the improvements obtainable with automation.

Time-resolved emission (TRE) systems are used in many FA labs for internal timing analysis of digital ICs. In this article, the authors explain how they use TRE systems to diagnose analog circuit failures as well. The key to their success is the use of an asynchronous trigger on the emission detector, which eliminates measurement error due to nonlinear distortion. A case study of an analog amplifier failure caused by a polysilicon short demonstrates the effectiveness of their technique.

This column reflects on the emergence of integrated fabless manufacturers (IFMs) in the semiconductor industry and the effect it will have on failure analysis. In the IFM environment, FA will likely play the same roles, as in design debug, qualification, yield, and customer returns, but with new challenges and expectations as explained in this guest column.

The 22nd European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF 2011) was held October 3 to 7, 2011, in Bordeaux, France. The conference concentrated on two main areas in electronics that concern designers, manufacturers, and users: (1) strategy for quality and reliability assessment of electronic circuits and systems, and (2) advanced analysis techniques for technology and product evaluation. This article reports on highlights of the technical program.

This column reviews a survey of the top ISTFA contributors from 1999 to 2008 and the topics addressed in their papers.

The inverted orientation of a flip-chip packaged die makes it vulnerable to optical attacks from the backside. This article discusses the nature of that vulnerability, assesses the threats posed by optical inspection tools and techniques, and provides insights on effective countermeasures.

The 39th International Symposium for Testing and Failure Analysis (ISTFA 2013) was held in San Jose, Calif., November 3-7, 2012. This article provides a summary of the keynote presentation, technical program, panel discussion, tutorials, User’s Group meetings, and equipment exposition.