Search Results for fault diagnosis

This is the second article in a two-part series on test-based failure analysis (TBFA). The first article, which appeared in the August 2001 issue of EDFA, discussed the need for automated diagnostics and the general concept of TBFA. This article discusses the steps involved in implementing a TBFA process and addresses the challenges that are likely to be encountered. It explains how to gather data required to link observed behavior to specific faults, how to set up and use fault dictionaries, and how to handle unmodeled as well as bridging faults. It also discusses the use of TBFA with conventional voltage and quiescent current (IDDQ) testing.

Although much traditional FA depends on physical observation to localize failures, electrical techniques are also important, particularly with advances in design for testability (DFT) on modern ICs. DFT structures combined with automated test equipment and algorithmic fault diagnosis facilitate a test-based fault localization (TBFL) approach to identify defect locations on ICs based on scan test patterns. This article and a companion piece in the November 2001 issue of EDFA provide an overview these methods and show how they can reduce the number of potential defect sites on a chip and, in some cases, identify defects that would be missed by other techniques.

The analysis of scan-based ICs is essentially split between two domains: that of the designer and that of the device analyst. Designers tend to operate within the confines of fault characterization, looking for defects within logic blocks or structures based on test data. Device analysts, on the other hand, are more concerned with physical aspects of the defect such as location, composition, and morphology. These separate worlds are beginning to merge, however, as this case study shows, streamlining the entire failure analysis and resolution process.

This article presents a recent breakthrough in the use of machine learning in semiconductor FA. For the first time, cell-internal defects in FinFETs have not only been detected and diagnosed, but also refined, clarified, and resolved using cell-aware diagnosis along with root cause deconvolution (RCD) techniques. The authors describe the development of the methodology and evaluate the incremental improvements made with each step.

Scan-based diagnostics produce high-confidence target lists of suspected faults associated with electrical fail signatures. Physical coordinates extracted from these lists serve as a guide for physical failure analysis. When certain conditions are met for the design database and pattern sets, the extraction can be automated and the analysis completed within minutes. The logic mapping flow is a natural extension of scan-based diagnosis with the potential to reach new levels of electrical failure analysis without the extensive data collection and resources associated with signature analysis. This article describes the logic mapping concept and how to implement the flow. It also presents the results of actual cases in which logic mapping was used.

Scan-logic diagnosis is used in industry for three main purposes: root-cause analysis, improving manufacturing processes, and improving designs. This article reviews the principles of scan-logic diagnosis and its applications in each of the three areas. It also discusses ongoing challenges and emerging approaches.

The inverted orientation of a flip-chip packaged die makes it vulnerable to optical attacks from the backside. This article discusses the nature of that vulnerability, assesses the threats posed by optical inspection tools and techniques, and provides insights on effective countermeasures.

This case study compares the FA success rate and turn-around time of traditional logic-only and true layout-aware scan diagnosis. It discusses the basic process flow, identifies key success factors, and evaluates physical FA and diagnostic test results obtained from six dies randomly selected from a 9.8 M-gate, seven-metal-layer ASIC manufactured in 90 nm technology. As shown, layout-aware diagnosis reduces the defect search area on the die, in some cases, by an order of magnitude, providing the means to diagnosis-driven yield improvements.

This column explains how machine learning is being used to diagnose electrical faults and identify potential hot spots and systematic defects during IC design.

This article explains how the success rate of in-line scan chain logic macros can be nearly doubled for certain types of failures with the help of laser voltage imaging and laser voltage probing. The authors provide background information on LVI, LVP, and scan chain logic macros and show how they are used to diagnose skip test, clock-type, and soft single-latch failures.

This article discusses the causes and effects of stuck-open faults (SOFs) in nanometer CMOS ICs. It addresses detection and localization challenges and explains how resistive contacts and vias and the use of damascene-copper processes contribute to the problem. It also discusses layout techniques that reduce the likelihood of SOF failures.

This article provides insights into the nature of IDDQ and timing defects and the challenges they present to failure analysts based on the findings of a Sematach study.

This article presents a comprehensive study of physical inspection and attack methods, describing the approaches typically used by counterfeiters and adversaries as well as the risks and threats created. It also explains how physical inspection methods can serve as trust verification tools and provides practical guidelines for making hardware more secure.

This article summarizes major discussion points from four User’s Group meetings held at the ISTFA 2009 conference. The topics addressed are "Optical Techniques: Growth and Limitations," "Resolution of Nanoprobing for 45 nm and Beyond: New Challenges," "FIB," and "Fast ASIC Fault Isolation: Efficiency and Accurate Resolution of Software-Based Fault Isolation."

Technologies relatively new to failure analysis, like time-correlated photon counting, electro-optical probing, antireflective (AR) coating, Schlieren microscopy, and superconducting quantum interference (SQUID) devices are being leveraged to create faster, more powerful tools to meet increasingly difficult challenges in failure analysis. This article reviews recent advances and research in fault isolation and circuit repair.

The ISTFA 2006 panel discussion focused on the integration of test and failure analysis, a topic that was originally addressed at ISTFA 2000. The goal of this year’s panel was to discuss the improvements made to the integration of test and failure analysis and to explore our capabilities for analyzing future technologies.

This column explains what it takes to set up and run a successful foundry-based failure analysis laboratory.

Wafer-level failure analysis plays an important role in IC fabrication, both in process development and yield enhancement. This article outlines the general flow for wafer-level FA and explains how it differs for memory and logic products. It describes the tools and procedures used for failure mode verification, electrical analysis, fault localization, sample preparation, chemical analysis, and physical failure analysis. It also discusses the importance of implementing corrective actions and tracking the results.

This article describes a yield-driven approach for characterizing IC logic failures at the wafer level and presents several case studies to demonstrate its versatility and assess its value.

A new product-like test chip developed by engineers at Carnegie Mellon University overcomes the current limitations in conventional test chip design. This article discusses the advantages of the new chip, called the CM-LCV, and presents experimental results showing how it achieves fault coverages comparable to or better than benchmarking designs.