Skip Nav Destination
Close Modal
Search Results for
fault diagnosis
Update search
Filter
- Title
- Authors
- Author Affiliations
- Full Text
- Abstract
- Keywords
- DOI
- ISBN
- EISBN
- Issue
- ISSN
- EISSN
- Volume
- References
Filter
- Title
- Authors
- Author Affiliations
- Full Text
- Abstract
- Keywords
- DOI
- ISBN
- EISBN
- Issue
- ISSN
- EISSN
- Volume
- References
Filter
- Title
- Authors
- Author Affiliations
- Full Text
- Abstract
- Keywords
- DOI
- ISBN
- EISBN
- Issue
- ISSN
- EISSN
- Volume
- References
Filter
- Title
- Authors
- Author Affiliations
- Full Text
- Abstract
- Keywords
- DOI
- ISBN
- EISBN
- Issue
- ISSN
- EISSN
- Volume
- References
Filter
- Title
- Authors
- Author Affiliations
- Full Text
- Abstract
- Keywords
- DOI
- ISBN
- EISBN
- Issue
- ISSN
- EISSN
- Volume
- References
Filter
- Title
- Authors
- Author Affiliations
- Full Text
- Abstract
- Keywords
- DOI
- ISBN
- EISBN
- Issue
- ISSN
- EISSN
- Volume
- References
NARROW
Format
Topics
Journal
Article Type
Date
Availability
1-20 of 47
Search Results for fault diagnosis
Follow your search
Access your saved searches in your account
Would you like to receive an alert when new items match your search?
1
Sort by
Journal Articles
Advancing Technology: Test-Based Failure Analysis – Part 2: Fault Diagnosis
Available to Purchase
EDFA Technical Articles (2001) 3 (4): 21–26.
Published: 01 November 2001
... with conventional voltage and quiescent current (IDDQ) testing. Copyright © ASM International® 2001 2001 ASM International bridging faults fault diagnosis IDDQ testing test-based failure analysis httpsdoi.org/10.31399/asm.edfa.2001-4.p021 EDFAAO (2001) 4:21-26 ©ASM International Test-Based Failure...
Abstract
View articletitled, Advancing Technology: Test-Based Failure Analysis – Part 2: <span class="search-highlight">Fault</span> <span class="search-highlight">Diagnosis</span>
View
PDF
for article titled, Advancing Technology: Test-Based Failure Analysis – Part 2: <span class="search-highlight">Fault</span> <span class="search-highlight">Diagnosis</span>
This is the second article in a two-part series on test-based failure analysis (TBFA). The first article, which appeared in the August 2001 issue of EDFA, discussed the need for automated diagnostics and the general concept of TBFA. This article discusses the steps involved in implementing a TBFA process and addresses the challenges that are likely to be encountered. It explains how to gather data required to link observed behavior to specific faults, how to set up and use fault dictionaries, and how to handle unmodeled as well as bridging faults. It also discusses the use of TBFA with conventional voltage and quiescent current (IDDQ) testing.
Journal Articles
Test-Based Failure Analysis – Part 1: Fault Models
Available to Purchase
EDFA Technical Articles (2001) 3 (3): 7–11.
Published: 01 August 2001
... diagnosis facilitate a test-based fault localization (TBFL) approach to identify defect locations on ICs based on scan test patterns. This article and a companion piece in the November 2001 issue of EDFA provide an overview these methods and show how they can reduce the number of potential defect sites...
Abstract
View articletitled, Test-Based Failure Analysis – Part 1: <span class="search-highlight">Fault</span> Models
View
PDF
for article titled, Test-Based Failure Analysis – Part 1: <span class="search-highlight">Fault</span> Models
Although much traditional FA depends on physical observation to localize failures, electrical techniques are also important, particularly with advances in design for testability (DFT) on modern ICs. DFT structures combined with automated test equipment and algorithmic fault diagnosis facilitate a test-based fault localization (TBFL) approach to identify defect locations on ICs based on scan test patterns. This article and a companion piece in the November 2001 issue of EDFA provide an overview these methods and show how they can reduce the number of potential defect sites on a chip and, in some cases, identify defects that would be missed by other techniques.
Journal Articles
Bringing Closer the Logical and Physical Worlds for Device Analysis: A Case Study
Available to Purchase
EDFA Technical Articles (2006) 8 (2): 22–27.
Published: 01 May 2006
... being detected. The exact tester cycle numbers for the failure were also identified in the failure log. A script was used to analyze the failing pin and cycle information to identify the failing flip-flops: scan flip-flops 2122, 2123. Information related to failure(s) was used in the fault diagnosis...
Abstract
View articletitled, Bringing Closer the Logical and Physical Worlds for Device Analysis: A Case Study
View
PDF
for article titled, Bringing Closer the Logical and Physical Worlds for Device Analysis: A Case Study
The analysis of scan-based ICs is essentially split between two domains: that of the designer and that of the device analyst. Designers tend to operate within the confines of fault characterization, looking for defects within logic blocks or structures based on test data. Device analysts, on the other hand, are more concerned with physical aspects of the defect such as location, composition, and morphology. These separate worlds are beginning to merge, however, as this case study shows, streamlining the entire failure analysis and resolution process.
Journal Articles
Machine Learning Inside the Cell to Solve Complex FinFET Defect Mechanisms with Volume Scan Diagnosis
Available to Purchase
EDFA Technical Articles (2019) 21 (1): 4–9.
Published: 01 February 2019
... in Fig. 2. Figure 2 also shows that the fault f1 (output of c2 stuck-at-1) can explain the failing test response, therefore diagnosis will correlate this with the physical layout of the net driven by c2 as well as its physical neighbors to come up with diagnosis suspects. For example, if this net...
Abstract
View articletitled, Machine Learning Inside the Cell to Solve Complex FinFET Defect Mechanisms with Volume Scan <span class="search-highlight">Diagnosis</span>
View
PDF
for article titled, Machine Learning Inside the Cell to Solve Complex FinFET Defect Mechanisms with Volume Scan <span class="search-highlight">Diagnosis</span>
This article presents a recent breakthrough in the use of machine learning in semiconductor FA. For the first time, cell-internal defects in FinFETs have not only been detected and diagnosed, but also refined, clarified, and resolved using cell-aware diagnosis along with root cause deconvolution (RCD) techniques. The authors describe the development of the methodology and evaluate the incremental improvements made with each step.
Journal Articles
Advancing Technology: Logic Mapping to Enhance Electrical Failure Analysis
Available to Purchase
EDFA Technical Articles (2001) 3 (4): 3–11.
Published: 01 November 2001
... die on the wafer before being categorized as a defect. Early logic mapping used scan-based diagnosis as the TBFL mechanism. Scan-based diagnostics provide a high confidence target list of suspected faults for a given electrical fail signature4,5. Physical coordinates can be extracted from this list...
Abstract
View articletitled, Advancing Technology: Logic Mapping to Enhance Electrical Failure Analysis
View
PDF
for article titled, Advancing Technology: Logic Mapping to Enhance Electrical Failure Analysis
Scan-based diagnostics produce high-confidence target lists of suspected faults associated with electrical fail signatures. Physical coordinates extracted from these lists serve as a guide for physical failure analysis. When certain conditions are met for the design database and pattern sets, the extraction can be automated and the analysis completed within minutes. The logic mapping flow is a natural extension of scan-based diagnosis with the potential to reach new levels of electrical failure analysis without the extensive data collection and resources associated with signature analysis. This article describes the logic mapping concept and how to implement the flow. It also presents the results of actual cases in which logic mapping was used.
Journal Articles
The Many Faces of Software Diagnosis
Available to Purchase
EDFA Technical Articles (2007) 9 (3): 6–16.
Published: 01 August 2007
...). Scan-logic diagnosis then tries to determine (a) the location of the fault, usually expressed in the form of net names; (b) the type of fault, for example, stuck-at, bridge, or open, whichever best describes the observed faulty behavior; and (c) a confidence value that indicates how accurately...
Abstract
View articletitled, The Many Faces of Software <span class="search-highlight">Diagnosis</span>
View
PDF
for article titled, The Many Faces of Software <span class="search-highlight">Diagnosis</span>
Scan-logic diagnosis is used in industry for three main purposes: root-cause analysis, improving manufacturing processes, and improving designs. This article reviews the principles of scan-logic diagnosis and its applications in each of the three areas. It also discusses ongoing challenges and emerging approaches.
Journal Articles
Security Assessment of IC Packaging Against Optical Attacks
Available to Purchase
EDFA Technical Articles (2021) 23 (2): 4–12.
Published: 01 May 2021
... al.: Laser Fault Attack on Physically Unclonable Functions, 2015 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC), IEEE, 2015, p. 85 96. 4. S.P. Skorobogatov and R.J. Anderson: Optical Fault Induction Attacks, International Workshop on Cryptographic Hardware and Embedded Systems...
Abstract
View articletitled, Security Assessment of IC Packaging Against Optical Attacks
View
PDF
for article titled, Security Assessment of IC Packaging Against Optical Attacks
The inverted orientation of a flip-chip packaged die makes it vulnerable to optical attacks from the backside. This article discusses the nature of that vulnerability, assesses the threats posed by optical inspection tools and techniques, and provides insights on effective countermeasures.
Journal Articles
Experiences with Layout-Aware Diagnosis—A Case Study
Available to Purchase
EDFA Technical Articles (2010) 12 (2): 12–18.
Published: 01 May 2010
.../siliconyield/. 4. K. Gearhardt, C. Schuermyer, and R. Guo: Improving Fault Isolation Using Iterative Diagnosis, Proc. Int. Symp. Test. and Failure Analysis (ISTFA), Nov. 7-9, 2008, pp. 39095. 5. D. Bodoh, A. Blakely, and T. Garyet: Diagnostic Fault Simulation for the Failure Analyst, Proc. Int. Symp. Test...
Abstract
View articletitled, Experiences with Layout-Aware <span class="search-highlight">Diagnosis</span>—A Case Study
View
PDF
for article titled, Experiences with Layout-Aware <span class="search-highlight">Diagnosis</span>—A Case Study
This case study compares the FA success rate and turn-around time of traditional logic-only and true layout-aware scan diagnosis. It discusses the basic process flow, identifies key success factors, and evaluates physical FA and diagnostic test results obtained from six dies randomly selected from a 9.8 M-gate, seven-metal-layer ASIC manufactured in 90 nm technology. As shown, layout-aware diagnosis reduces the defect search area on the die, in some cases, by an order of magnitude, providing the means to diagnosis-driven yield improvements.
Journal Articles
Artificial Intelligence in Electronic Design Automation Assisting Physical Failure Analysis
Available to Purchase
EDFA Technical Articles (2018) 20 (3): 54–55.
Published: 01 August 2018
...Yu Huang This column explains how machine learning is being used to diagnose electrical faults and identify potential hot spots and systematic defects during IC design. Copyright © ASM International® 2018 2018 ASM International AI-assisted diagnosis EDA tools machine learning...
Abstract
View articletitled, Artificial Intelligence in Electronic Design Automation Assisting Physical Failure Analysis
View
PDF
for article titled, Artificial Intelligence in Electronic Design Automation Assisting Physical Failure Analysis
This column explains how machine learning is being used to diagnose electrical faults and identify potential hot spots and systematic defects during IC design.
Journal Articles
LVI and LVP Applications in In-Line Scan Chain Failure Analysis
Available to Purchase
EDFA Technical Articles (2016) 18 (4): 4–14.
Published: 01 November 2016
..., involving tester-based fault isolation[3,4] and software-based scan diagnosis.[5,6] Thus, it is very important to have an in-line scan chain logic macro implemented for early detection of the logic circuit weak points during technology development. Furthermore, THE COMBINATION OF LVI AND LVP APPLICATION...
Abstract
View articletitled, LVI and LVP Applications in In-Line Scan Chain Failure Analysis
View
PDF
for article titled, LVI and LVP Applications in In-Line Scan Chain Failure Analysis
This article explains how the success rate of in-line scan chain logic macros can be nearly doubled for certain types of failures with the help of laser voltage imaging and laser voltage probing. The authors provide background information on LVI, LVP, and scan chain logic macros and show how they are used to diagnose skip test, clock-type, and soft single-latch failures.
Journal Articles
What Ever Happened to the Famous CMOS Stuck-Open Fault (aka The Memory Fault)?
Available to Purchase
EDFA Technical Articles (2006) 8 (3): 12–17.
Published: 01 August 2006
.... Tseng, and E.J. McCluskey: Diagnosis for Sequence-Dependent Chips, VLSI Test Symp., April 2002, pp. 187-92. 7. X. Fan, W. Moore, C. Hora, and G. Gronthoud: A Novel Stuck-At-Based Method for Transistor Stuck-Open Fault Diagnosis with Stuck-At Model, Paper 16.1, Int. Test Conf. (ITC), Nov. 2005. 8. B...
Abstract
View articletitled, What Ever Happened to the Famous CMOS Stuck-Open <span class="search-highlight">Fault</span> (aka The Memory <span class="search-highlight">Fault</span>)?
View
PDF
for article titled, What Ever Happened to the Famous CMOS Stuck-Open <span class="search-highlight">Fault</span> (aka The Memory <span class="search-highlight">Fault</span>)?
This article discusses the causes and effects of stuck-open faults (SOFs) in nanometer CMOS ICs. It addresses detection and localization challenges and explains how resistive contacts and vias and the use of damascene-copper processes contribute to the problem. It also discusses layout techniques that reduce the likelihood of SOF failures.
Journal Articles
Failure Analysis of Timing and IDDQ-only Failures from the SEMATECH Test Methods Experiment
Available to Purchase
EDFA Technical Articles (2000) 2 (1): 4–27.
Published: 01 February 2000
.... 100Q diagnosis did point to the defect site. but the diagnostic resolution was relatively poor; it was only 1'k'UTOWOO down to 15 1000 faults. 111e 1000 measurctllCnts are shown in Figure 2. The high current St.ltes were the oncs where the defective node (A in Fig. Ia) was driven to logical '0...
Abstract
View articletitled, Failure Analysis of Timing and IDDQ-only Failures from the SEMATECH Test Methods Experiment
View
PDF
for article titled, Failure Analysis of Timing and IDDQ-only Failures from the SEMATECH Test Methods Experiment
This article provides insights into the nature of IDDQ and timing defects and the challenges they present to failure analysts based on the findings of a Sematach study.
Journal Articles
Failure Analysis for Hardware Assurance and Security
Available to Purchase
EDFA Technical Articles (2019) 21 (3): 16–24.
Published: 01 August 2019
...: Sparse Imaging for Fast Electron Microscopy, Proc. SPIE 8657, Computational Imaging XI, February 2013. 11. C. Boit, C. Helfmeier, and U. Kerst: Security Risks Posed by Modern IC Debug and Diagnosis Tools, 2013 Workshop on Fault Diagnosis and Tolerance Cryptography (FDTC), IEEE, 2013, p. 3-11. 12...
Abstract
View articletitled, Failure Analysis for Hardware Assurance and Security
View
PDF
for article titled, Failure Analysis for Hardware Assurance and Security
This article presents a comprehensive study of physical inspection and attack methods, describing the approaches typically used by counterfeiters and adversaries as well as the risks and threats created. It also explains how physical inspection methods can serve as trust verification tools and provides practical guidelines for making hardware more secure.
Journal Articles
ISTFA 2009 User’s Group Discussion Summaries
Available to Purchase
EDFA Technical Articles (2010) 12 (2): 20–28.
Published: 01 May 2010
... addressed software-based fault isolation from various positions. The consensus was that software-based methods, in particular diagnosis, are mature technologies and are valuable additions to the engineer s toolbox. Key to nearly all the presentations was the inclusion of layout information in one form...
Abstract
View articletitled, ISTFA 2009 User’s Group Discussion Summaries
View
PDF
for article titled, ISTFA 2009 User’s Group Discussion Summaries
This article summarizes major discussion points from four User’s Group meetings held at the ISTFA 2009 conference. The topics addressed are "Optical Techniques: Growth and Limitations," "Resolution of Nanoprobing for 45 nm and Beyond: New Challenges," "FIB," and "Fast ASIC Fault Isolation: Efficiency and Accurate Resolution of Software-Based Fault Isolation."
Journal Articles
Roadmaps: Advanced Fault Isolation Techniques
Available to Purchase
EDFA Technical Articles (1999) 1 (3): 6–17.
Published: 01 August 1999
... of a fault-based only on its electrical effects on the circuit. This approach can range from a fully manual analysis to a highly structured and automated diagnosis based on special strategically placed diagnostic circuits and a unique test method. Manual diagnosis, even if supported by sophisticated data...
Abstract
View articletitled, Roadmaps: Advanced <span class="search-highlight">Fault</span> Isolation Techniques
View
PDF
for article titled, Roadmaps: Advanced <span class="search-highlight">Fault</span> Isolation Techniques
Technologies relatively new to failure analysis, like time-correlated photon counting, electro-optical probing, antireflective (AR) coating, Schlieren microscopy, and superconducting quantum interference (SQUID) devices are being leveraged to create faster, more powerful tools to meet increasingly difficult challenges in failure analysis. This article reviews recent advances and research in fault isolation and circuit repair.
Journal Articles
Test and Failure Analysis: Have We Progressed in Bringing Them Together?
Available to Purchase
EDFA Technical Articles (2007) 9 (1): 24–25.
Published: 01 February 2007
... infrastructure. Bridging the gap be- tween diagnosis and fault isolation by performing local searches instead of global ones, thus narrowing the fault to a specific region, will help identify a starting point for failure analysis. In summary, the panel identified different factors that will improve...
Abstract
View articletitled, Test and Failure Analysis: Have We Progressed in Bringing Them Together?
View
PDF
for article titled, Test and Failure Analysis: Have We Progressed in Bringing Them Together?
The ISTFA 2006 panel discussion focused on the integration of test and failure analysis, a topic that was originally addressed at ISTFA 2000. The goal of this year’s panel was to discuss the improvements made to the integration of test and failure analysis and to explore our capabilities for analyzing future technologies.
Journal Articles
The Failure Analysis Lab behind the Foundry Business
Available to Purchase
EDFA Technical Articles (2011) 13 (4): 50–51.
Published: 01 November 2011
... diagnosis data. A foundry FA lab can possibly handle dynamic fault isolation tasks by software, hardware, and the analyzed diagnosis data supported by customer engineering resources under a design-for-manufacturing concept. Layout navigation and net-list tracking are essential capabilities empowering...
Abstract
View articletitled, The Failure Analysis Lab behind the Foundry Business
View
PDF
for article titled, The Failure Analysis Lab behind the Foundry Business
This column explains what it takes to set up and run a successful foundry-based failure analysis laboratory.
Journal Articles
Wafer-Level Failure Analysis Process Flow
Available to Purchase
EDFA Technical Articles (2010) 12 (2): 4–11.
Published: 01 May 2010
.... The representative technique in this stage is an electrical fault isolation method called scan diagnosis, (continued on page 6) Overview of the YieldEnhancement Loop For the purpose of this general introduction, assume that the failure analyst is engaged in a yield-enhancement activity. Thus, a generalized yield...
Abstract
View articletitled, Wafer-Level Failure Analysis Process Flow
View
PDF
for article titled, Wafer-Level Failure Analysis Process Flow
Wafer-level failure analysis plays an important role in IC fabrication, both in process development and yield enhancement. This article outlines the general flow for wafer-level FA and explains how it differs for memory and logic products. It describes the tools and procedures used for failure mode verification, electrical analysis, fault localization, sample preparation, chemical analysis, and physical failure analysis. It also discusses the importance of implementing corrective actions and tracking the results.
Journal Articles
Yield-Oriented Logic Failure Characterization for FA Prioritization
Available to Purchase
EDFA Technical Articles (2014) 16 (3): 4–12.
Published: 01 August 2014
... to achieve this is prioritization. Prioritization is a standard practice in software fault isolation (FI) tools such as static random ac- (a) (b) Fig. 1 (a) SRAM bitmapping and (b) volume logic scan diagnosis workflows 4 Electronic Device Failure Analysis cess memory (SRAM) bitmapping and electronic device...
Abstract
View articletitled, Yield-Oriented Logic Failure Characterization for FA Prioritization
View
PDF
for article titled, Yield-Oriented Logic Failure Characterization for FA Prioritization
This article describes a yield-driven approach for characterizing IC logic failures at the wafer level and presents several case studies to demonstrate its versatility and assess its value.
Journal Articles
An Automated Methodology for Logic Characterization Vehicle Design
Available to Purchase
EDFA Technical Articles (2019) 21 (1): 12–19.
Published: 01 February 2019
..., and presents experimental results showing how it achieves fault coverages comparable to or better than benchmarking designs. A new product-like test chip developed by engineers at Carnegie Mellon University overcomes the current limitations in conventional test chip design. This article discusses...
Abstract
View articletitled, An Automated Methodology for Logic Characterization Vehicle Design
View
PDF
for article titled, An Automated Methodology for Logic Characterization Vehicle Design
A new product-like test chip developed by engineers at Carnegie Mellon University overcomes the current limitations in conventional test chip design. This article discusses the advantages of the new chip, called the CM-LCV, and presents experimental results showing how it achieves fault coverages comparable to or better than benchmarking designs.
1