Search Results for failure rate

The reliability of a component is the probability that it will perform its function under specified conditions for a specified length of time. Key considerations in defining and designing reliability tests are reviewed in this article, which also discusses the interpretation of test results.

Failure analysis is the study and presentation of observable or measurable phenomena. Risk assessment, on the other hand, is when root causes are studied to predict the potential for future failures. In this article, the author describes a structured problem-solving approach that consists of failure analysis, risk assessment, and advanced modeling. A case study is also presented in which the probability of future failures, due to a delamination defect, is determined based on field returns.

Stress voiding has re-emerged as a concern in advanced metal systems with their reduced dimensions and multilayer designs. Unless analysts are familiar with the physics and history of stress voids in ICs, chances are they will go unnoticed. This article discusses the basic cause of stress cracks and the clues that give them away.

Passive voltage contrast (PVC) has traditionally been used by semiconductor engineers for end-of-line post-mortem analysis. PVC distinguishes between open and short structures and is both nondestructive and noncontact. When applied during process development for in-line characterization, it allows wafers to be examined at multiple points, where electrical probing might not be feasible. This provides feedback on the cumulative effect of the process on critical parameters such as oxide integrity and can reduce development cycle times because wafers do not have to be deprocessed in order to determine the exact location of failures. Two case studies are presented in this article, demonstrating the use of PVC in a process development environment.

This article explains why it has become necessary for equipment builders to analyze passive component failures and how the findings should be reported to manufacturers. It describes the general approach and steps involved in analyzing passive component failures and the methods and equipment used. It also explains how an actual failure involving a microwave switch was resolved.

Unit level traceability (ULT) is a powerful tool that allows complete die histories to be accessed in the course of testing and analysis. It is especially useful for identifying the likely causes of microprocessor failures and in cases where failure analysis resources are limited. In the article, the author explains how he used ULT in the investigation of a 0.25-µm CMOS processor. Using the ULT of the die, he discovered a failure signature based on die location on the wafer. One root cause of failure was traced to cross-field variation in the lithography process due to marginal focus control. Another failure, observed after burn-in, was traced to the presence of residual titanium left after metal etch.

Scan-logic diagnosis is used in industry for three main purposes: root-cause analysis, improving manufacturing processes, and improving designs. This article reviews the principles of scan-logic diagnosis and its applications in each of the three areas. It also discusses ongoing challenges and emerging approaches.

A guest columnist shares some of the lessons learned in the course of his career. The wisdom contained in these lessons can be summed up as follows: look at the problem from different perspectives, believe the data, and don’t give up too soon.

This columnn explores the idea that insights into the root cause of increasingly complex failures may be hidden in unanswered questions from past analyses, indicating that there might be more value in previous files than once thought.

Failure analysis requires a working knowledge of physics, technology, materials, manufacturing practices, analytical techniques, and more. It is difficult to imagine what failure analysis would be like if all the laws of physics were perfectly apparent and all the challenges of sample preparation and testing were removed. Eliminating those considerations, failure analysis would be more like Sudoku. Sudoku is a simple number puzzle enjoyed by both children and adults. The simplicity of Sudoku compared to failure analysis is the point. Although Sudoku is starkly simple, the process is challenging to the best of us. Good and bad problem-solving practices are clearly exposed by the experience of solving a few Sudoku puzzles. Some insights that are brilliantly clear in Sudoku are equally true in failure analysis.

This study investigates the corrosion effects on SAC305 lead-free solder joints under varying temperature and salinity conditions. Researchers exposed chip resistors soldered with SAC305 on FR4 boards to salt spray environments at three temperatures (25, 35, and 45 °C) and three salinity rates (3.5%, 5%, and 6.5% NaCl). While no electrical failures occurred during testing, mechanical strength decreased significantly with increasing corrosion time, temperature, and NaCl concentration. Through optical microscopy and SEM-EDX analysis, the researchers identified that the corroded areas contained primarily Sn, O, and Cl-. By correlating shear force measurements with the percentage of corroded solder joint area, they established a failure criterion at approximately 61% corroded surface area. This criterion was validated with additional testing, providing a practical measure for predicting mechanical failure in SAC solder joints exposed to marine environments.

Reflecting back on the past 45 years in semiconductor failure analysis, the columnist notes that the trend lines have deviated little over that time. He then goes on to point out the relatively few discontinuities, the latest of which, the emergence of the “invisible defect,” takes him back to the beginning of his journey.

This column presents a detailed flowchart for failure analysis.

Electromigration is a wearout mechanism that contributes significantly to IC failures. This article discusses the causes and effects of this often overlooked failure mode and presents practical guidelines to help analysts determine whether or not electromigration is the cause of a particular failure. It also discusses the differences between aluminum and copper electromigration.

This article explains how the success rate of in-line scan chain logic macros can be nearly doubled for certain types of failures with the help of laser voltage imaging and laser voltage probing. The authors provide background information on LVI, LVP, and scan chain logic macros and show how they are used to diagnose skip test, clock-type, and soft single-latch failures.

This installment of Ask the Expert discusses the causes of electrolytic capacitor failures and how they are determined. It also addresses a question regarding hot spots caused by latch-up and how to locate them in the presence of background current.

The susceptibility of ICs to electromagnetic interference is a growing concern for both designers and failure analysts. This article discusses the causes and effects of transient electromagnetic interference and the factors that influence electromagnetic susceptibility. It explains how to determine susceptibility based on transient pulse testing and presents and interprets the test results of three automotive ICs.

In most cases, microelectronic failure analysis is rooted in the observation of voltage, either as logic levels or as time-based waveforms. This is due largely to the ease of making such measurements. As a result, current measurement is often overlooked. This article discusses aspects of current measurement that can be used during fault localization, often providing information that cannot be obtained by other means.

It seems that scaling of chip technology according to Moore’s Law will continue for digital functionalities (logic and memory); however, increasing system integration on chip and package levels, called “More than Moore,” has been observed in the past several years. This strong trend in the worldwide semiconductor industry enables more functionality, diversification, and higher value by creating smart microsystems. This article discusses the many challenges faced in FA of 3-D chips, where well-staffed and equipped FA labs are essential. Furthermore, FA is becoming an important strategic enabling factor for new products, not just another “cost factor.”

The organizer and moderator of the ISTFA 2007 panel discussion on failure analysis and testing of medical devices provide a summary of the discussion topics and areas of focus.