Wafer-level failure analysis plays an important role in IC fabrication, both in process development and yield enhancement. This article outlines the general flow for wafer-level FA and explains how it differs for memory and logic products. It describes the tools and procedures used for failure mode verification, electrical analysis, fault localization, sample preparation, chemical analysis, and physical failure analysis. It also discusses the importance of implementing corrective actions and tracking the results.

Many standard physical failure site isolation techniques require an electrical stimulus to drive test devices into a failing condition. This function has been provided by bench test electronics for some time, but increasing device complexity is causing a migration to more sophisticated equipment such as pattern generators and logic analyzers. In anticipation of further increases in pin count and density, a new class of small footprint testers is emerging. These portable systems, called ASIC verification testers, facilitate the transfer of ATE test programs to failure analysis laboratories at relatively low cost.

Faster time-to-production of a new product is the common goal of design houses and foundries. This article demonstrates how foundries can contribute through post silicon validation, which allows design houses to focus on more complicated issues.

This article presents an automation workflow for the development of analog and mixed-signal devices similar to the two-stage process used for the design and verification of logic ICs. The use of a co-simulation interface makes it possible to build and verify failure models.

Soft electrical failures caused by monograin defects can have a significant impact on yield in technology nodes below 40 nm. Moreover, the failures are hard to identify and the defects give very few signatures during localization testing. In this article, the authors explain how they used nanobeam diffraction with automated crystal orientation and phase mapping to pinpoint a single grain orientation causing the problem and, as a result, are now able to recognize the symptoms of this type of failure, observe the defect, and limit the impact on electrical timing margins through both design and process corrections.

Experiments to assess microelectromechanical systems (MEMS) test their functionality and materials properties. These experiments provide knowledge and insight into MEMS failure modes and potential pathways to improve the lifetime of MEMS devices. This article demonstrates the use of optical microscopy and SEM analysis to determine various causes of failure in MEMS devices.

Thin film anomalies cause many device failures but they are often difficult to see. In this article, the authors explain how they found and identified an 8 to 10 nm film of tantalum causing pin shorts in a majority of ASIC modules from a particular lot. Initial attempts to delayer some of the failed modules resulted in the loss of the failure signal. It was then decided to use a focused ion beam to selectively mill through the interlayer dielectric. During milling, a secondary electron image revealed anomalous material between the fingers of a power transistor, which was subsequently identified as tantalum. Such defects, as the authors explain, are common in damascene processes when materials are not properly removed during etching.

Scanning microwave impedance microscopy (sMIM) is an electrical measurement technique that can be used to determine dopant profiles in semiconductor devices. This article describes the basic setup and implementation of the method and demonstrates its use in the cross-sectional analysis of NMOS power transistors.

The tools of the trade in semiconductor failure analysis have advanced rapidly over the past few decades, bringing major improvements in imaging, deprocessing, and materials analysis. In contrast to the progress made in physical FA, little attention has been given to the failure analysis process itself. This article shows through case studies how simple oversights and misunderstandings can lead to costly mistakes. It also defines basic FA concepts and presents a failure analysis sequence, describing each step along with common pitfalls and best practices.

It seems that scaling of chip technology according to Moore’s Law will continue for digital functionalities (logic and memory); however, increasing system integration on chip and package levels, called “More than Moore,” has been observed in the past several years. This strong trend in the worldwide semiconductor industry enables more functionality, diversification, and higher value by creating smart microsystems. This article discusses the many challenges faced in FA of 3-D chips, where well-staffed and equipped FA labs are essential. Furthermore, FA is becoming an important strategic enabling factor for new products, not just another “cost factor.”

This article presents a comprehensive study of physical inspection and attack methods, describing the approaches typically used by counterfeiters and adversaries as well as the risks and threats created. It also explains how physical inspection methods can serve as trust verification tools and provides practical guidelines for making hardware more secure.

This article presents a complete business model for Failure Analysis (FA) as a high tech provider in the world of microelectronics. Part I introduces the fundamentals of such a model. It starts with the definitions of a business process, and then the analysis flows are presented. Finally, a Key Performance Indicator (KPI) based operation is developed. Part II of this article will appear in the next issue of EDFA, and it will address the implementation of such a model in an FA lab. It discusses the interdependencies of workload and cycle times—the pipeline management. This opens the path to quantitative target setting agreements with customers. A complete system builds a database that can calculate all the parameters for an FA lab tailored exactly to the demand of the customer. Such a database acts as a reference lab and represents best FA practice.

Root-cause analysis and FA work hand-in-hand to identify the source of a problem, gather relevant data, and resolve the issue. However, even experienced professionals can succeed in FA while failing in the outcome. This article explains how to avoid common traps, dead ends, and faulty thought processes in the search for root causes.

Counterfeiting continues to be a concern in the electronics industry, particularly for microprocessors, memory chips, and high temperature range ICs. This article provides an understanding of the extent of the problem, identifies frequently copied parts, and proposes measures to help keep counterfeiters in check.

The Assembly Analytical Forum (AAF) is an organization under the auspices of the Sematech Quality Council. The AAF charter is to develop Packaging Analytical Roadmaps five to ten years into the future that are consistent with the International Technology Roadmap for semiconductors (ITRS). At ISTFA 2003, the AAF will convene with interested conference attendees to review, edit, and validate a white paper that will quantify critical gaps in the current suite of test, measurement, and characterization tools used in the semiconductor industry and provide recommendations on how to address them. The intent is to update the document biannually and review it in numerous industry venues to ensure its relevancy and utility. This article is somewhat of a preview to the Rev 0 AAF white paper.

This article examines the phenomenon of time-dependent dielectric breakdown (TDDB) in ultrathin gate oxide films and explains why it is no longer considered a catastrophic failure in MOSFET-containing ICs.

Flip chip mounted devices are difficult debug using conventional FIB tools because their internal circuitry is not easily accessible. New flip chip focused ion beam (FC FIB) systems overcome this limitation, however, making it possible to access circuits from the backside through the bulk silicon. In this article, the authors explain how they used the new system to gain access to signal lines for backside waveform acquisition. They also describe some of the procedures they developed to repair and modify flip chip circuits from the backside and prepare cross-section samples from the backside for failure analysis and characterization.

Over the last few years, new challenges increased the pressure on packaging and assembly analytical resources. Reduced product development cycle time, increased market segmentation, new package and die level materials, ever shrinking device geometries, and fully enabled technologies (i.e. with thermal, retention, and EMI solutions) created these new pressures on fault isolation/failure analysis efforts and package development.

This article provides a detailed overview of silicon characterization and debug process, describing the intent of each step, the challenges involved, and the FA tools and techniques used. It also discusses the difference between electrical and functional failures, the implementation and use of on-chip debugging resources, the important role of schmoo plots.

This article presents best practices and procedures for analyzing printed circuit board assembly failures. It discusses the role of electrostatic discharge and electrical overstress, the increasing complexity of ball grid arrays and buried vias, the challenges associated with lead-free solder processes, and the problems caused by counterfeit components flowing into our supply lines. It also includes a summary of the tools available to failure analysts and how they are best put to use