Search Results for failure debug

Faster time-to-production of a new product is the common goal of design houses and foundries. This article demonstrates how foundries can contribute through post silicon validation, which allows design houses to focus on more complicated issues.

This article describes a yield-driven approach for characterizing IC logic failures at the wafer level and presents several case studies to demonstrate its versatility and assess its value.

This article provides a detailed overview of silicon characterization and debug process, describing the intent of each step, the challenges involved, and the FA tools and techniques used. It also discusses the difference between electrical and functional failures, the implementation and use of on-chip debugging resources, the important role of schmoo plots.

This article explains how hardware and software enhancements bring new capabilities to one of the most widely used soft-defect localization techniques. It discusses the basic concept of electrically enhanced laser-assisted device alteration (EeLADA) and demonstrates its use on different types of soft and hard defects. It also discusses the relative advantages of hardware and software implementations.

This column reflects on the emergence of integrated fabless manufacturers (IFMs) in the semiconductor industry and the effect it will have on failure analysis. In the IFM environment, FA will likely play the same roles, as in design debug, qualification, yield, and customer returns, but with new challenges and expectations as explained in this guest column.

This article explains how laser voltage probing (LVP) can be used to analyze combinational logic circuits. The authors describe how the technique is aided by the development and use of a waveform library and a corresponding truth table. They also present a case study in which the new technique is used to isolate faults in a combinational logic circuit consisting of multiple gates.

At a Silicon Valley panel discussion on bringing new ICs to market, there was no mention by anyone onstage of a debug strategy, let alone its importance. This month’s guest columnist offers his insight on why that is and what should be done about it.

Laser voltage probing (LVP), an IR-based technique, facilitates through-silicon signal waveform acquisition and high frequency timing measurements from active p-n junctions on CMOS ICs. The ICs can be in flip-chip as well as wire-bond packages with backside access to the IC. As the article explains, LVP significantly improves silicon debug and failure analysis throughput time compared to electron-beam probing because it eliminates the need for backside trenching and probe-hole generating operations.

By providing timing information and throughput as device complexities and operating frequencies were rapidly increasing, the e-beam prober, which integrated CAD navigation and waveform measurements while enabling the user to almost disregard the technology “under the hood,” was the required tool for IC design debug from the late 1980s to the early 2000s. The history, successes, innovations, mistakes, and possible future of this workhorse tool are visited and described.

The EDFAS Board of Directors (BOD) has undertaken an initiative to help drive the development of failure analysis methods as leading-edge semiconductor technology approaches the sub-20 nm regime. To streamline efforts and leverage existing work, the BOD recently surveyed its constituency to gauge their opinions on the capability gaps identified by the Sematech councils. This article briefly discusses the methodology of the survey and provides a summary of the responses along with key findings.

Shmoo plotting began in the early 1970s and still has wide use in characterizing device performance against various parameters. Typically, Shmoo plots measure device frequency or cycle time versus voltage. The debug described in this article focused on problems (holes) in Shmoo plots discovered while designing a 637-MHz microprocessor. This problem had two distinct phases as the microprocessor design migrated from an older CMOS process technology into a newer, faster one. Resolution of the problem, as the article explains, required advanced DFD/DFT (design for debug/design for test) techniques and FIB circuit edit to resolve.

Flip chip mounted devices are difficult debug using conventional FIB tools because their internal circuitry is not easily accessible. New flip chip focused ion beam (FC FIB) systems overcome this limitation, however, making it possible to access circuits from the backside through the bulk silicon. In this article, the authors explain how they used the new system to gain access to signal lines for backside waveform acquisition. They also describe some of the procedures they developed to repair and modify flip chip circuits from the backside and prepare cross-section samples from the backside for failure analysis and characterization.

3-D silicon integration is reaching the point where it may be deployed. 3-D silicon integration is different from 3-D packaging in that 3-D packaging involves whole packaged chips, and each chip can still be tested individually throughout the manufacturing and assembly process, such as at wafer test, before and after packaging, and before and after integration into a complex chip assembly. Thus, methods used to test, debug, and verify multichip modules are generally extensible into the 3-D packaging space. For 3-D silicon integration using through-silicon vias, the issue is debug or test access to an individual die in the stack. This article reports on efforts by an IEEE P1838 Working Group to develop a per die standard.

ICs designed for portable devices often make use of reverse-body bias (RBB) modes to limit leakage currents. The added complexity of RBB support circuitry presents a challenge during IC characterization and debug. This article discusses the nature of the problem and explains how to identify irregularities in circuits operating in the body-biased condition using standard debug tools with simple modifications. It describes some of the bugs discovered in an actual examination and explains how they were diagnosed by analyzing I-V curve traces and infrared emission microscopy (IREM) images.

Scan chains help detect and identify failures in integrated circuits, but they are also susceptible to failure themselves. When scan chains break, it does not necessarily render them useless. Normally, scan chains can be debugged and diagnosed so that they can be fixed or used while masking out vector bits associated with broken or corrupted portions of the chain. This article describes the different ways that scan chains can break and how it tends to affect their performance. It explains how to repair various types of scan chain failures or at least regain partial use for limited testing purposes.

This column provides some thoughts on the cultivation of ideas and the conditions that must exist in a failure analysis laboratory to allow fledgling methods to become deeply rooted, flourishing techniques. As an example, the author recounts the introduction and subsequent development of resistive interconnect localization (RIL) is his lab.

This article discusses recent improvements in FIB circuit edit as well as general uses and optimization techniques.

This column describes a unique arrangement between two IC manufacturers that built and share a state-of-the-art failure analysis laboratory. The lab is dedicated to helping the two companies characterize their new technologies, debug new designs, measure IC performance, find defects responsible for yield loss, and improve product reliability. In addition to discussing the technical capabilities of the lab, our guest columnist also explains how the lab is funded and managed.

Laser-assisted copper deposition provides a key technology for analyzing complex packaging and integrated circuit challenges. Laser-based copper deposition techniques have been shown to be useful in combination with traditional FIB techniques to improve resistivity, deposition rate, and timing.

Scan-based diagnostics produce high-confidence target lists of suspected faults associated with electrical fail signatures. Physical coordinates extracted from these lists serve as a guide for physical failure analysis. When certain conditions are met for the design database and pattern sets, the extraction can be automated and the analysis completed within minutes. The logic mapping flow is a natural extension of scan-based diagnosis with the potential to reach new levels of electrical failure analysis without the extensive data collection and resources associated with signature analysis. This article describes the logic mapping concept and how to implement the flow. It also presents the results of actual cases in which logic mapping was used.