This article shows how 3D XRM can be applied to nondestructively detect non-optimized assembly processes that can influence local stresses and overall device reliability. This makes it useful for process development and failure analysis. When used along with AI training models, 3D XRM can achieve analysis of highly integrated packaging structures with reasonable throughput for process validation and error correction guidance.

This article presents a control model that may have application to automated wafer-level die testing and characterization. Mimicking the behavior of a dragonfly in pursuit of prey, the model implements a form of proportional navigation that optimizes interception trajectories based on feedforward error signals derived from image data.

This column assesses the near-term challenges associated with quantum computing, noting that 15 years is an optimistic estimate for commercially viable quantum cloud computing. In the midst of the struggle, however, there is also opportunity, particularly in metrology and component development.

Analog computing is an important step in taking neural net processing to the next level. However, as this column explains, reliability is intimately linked to performance and efficiency in analog systems, more so than in any modern digital system, and further work is required to understand the relationship.

The problem of constructing reliable systems out of unreliable components is usually dealt with through a combination of redundancy and early retirement. This article assesses the potential of an intelligent failure prediction system that depends more on diagnostic data and analytics than built-in redundancy and costly replacement.

This article reviews recent work aimed at characterizing soft-error effects in SRAM circuits fabricated with bulk silicon FinFETs. Accelerated tests were conducted on 6T planar and FinFET-based SRAM cells by exposing them to high-energy neutrons and alpha particles. Based on test results and simulations, the authors show that soft-error rates are much lower in FinFET devices because the geometry of the fins limits charge collection.

The organizer and moderator of the ISTFA 2007 panel discussion on failure analysis and testing of medical devices provide a summary of the discussion topics and areas of focus.

Diagnostic failure analysis tools provide essential information about where a defect is located and what materials are present, but that information must be combined with other data to establish cause and corrective action. Mistakes made at this stage of the investigation can be extremely costly. This article identifies some of the pitfalls and traps that failure analysts can fall into and explains how to avoid them. It provides three examples of misdiagnosed failures and helps readers to see what led analysts astray.

This article presents and evaluates a calibration method that significantly improves the spectral information that can be extracted from photon emission signals obtained from semiconductor devices. Step-by-step instructions are given for calibrating photon emission microscopes for specific measurements such as device parameters and material band gap. The article also discusses the types of errors that can occur during calibration. Although the procedure presented is used on InGaAs sensors, it applies to all common photon emission detectors.

Researchers at Boston University have made significant improvements in the resolution that can be achieved with backside imaging techniques. In this article, they explain how they optimize lateral and longitudinal resolution of IR-based methods using aplanatic solid immersion lenses in combination with adaptive optics that correct for aberrations, interferometry to improve signal-to-noise ratios, vortex beams that overcome diffraction limitations, and image reconstruction techniques based on prior knowledge about the objects under investigation.

This article discusses the causes and effects of stuck-open faults (SOFs) in nanometer CMOS ICs. It addresses detection and localization challenges and explains how resistive contacts and vias and the use of damascene-copper processes contribute to the problem. It also discusses layout techniques that reduce the likelihood of SOF failures.

This article discusses the tradeoffs associated with minimizing beam dose in a scanning transmission electron microscope (STEM) and explains how to reduce beam exposure through subsampling and inpainting, a signal reconstruction technique that optimizes image quality and resolution. Although the method is described in the context of STEM imaging, it applies to any scanned imaging system.

This article, the first in a multi-part series, describes how to finely control remaining silicon thickness (RST) through the correction of mechanical surface profiles using multipoint thickness measurements. It explains why multipoint thickness measurements are necessary and discusses the realities of silicon thickness measurements. With careful processing, cleaning, and RST measurements, samples can be reliably processed to a 50 μm thickness with a variation of +/- 2.5 μm across the majority of the die.

This article describes a hardware metering fingerprint technique, called the memometer, that addresses supply chain integrity issues with field-programmable gate arrays (FPGAs). The memometer is a physically unclonable function (PUF) based on cross-coupled lookup tables that overcomes manufacturing memory power-on preset. The fingerprints are not only unique, but also reliable with average hamming distances close to the ideal values of 50% (interchip) and 0% (intrachip). Instead of having one fingerprint per device, the memometer makes provision for hundreds with the potential for more.

Stress voiding is an insidious IC failure mechanism that can be difficult to identify and arrest. It is of particular concern to those who produce and test ICs with aluminum-alloy interconnects or who assess the reliability of legacy devices with long service life. This article explains how stress voids form and grow and how to determine the root cause by amassing physical evidence and ruling out other failure mechanisms. The key to differentiating stress voiding from other types of failures is recognizing that is the result of three distinct physical phenomena, stress, nucleation, and diffusion, all of which must be confirmed before attempting to make process corrections.

Virtually all semiconductor materials exhibit Raman scattering which results in a frequency shift in photon energy. In this article, the authors explain how they harness this mechanism to measure the temperature of submicron structures and thereby produce high-resolution temperature maps. They review the basic theory of Raman scattering and present application examples involving high-bandgap materials as well as silicon devices.

Scan chains help detect and identify failures in integrated circuits, but they are also susceptible to failure themselves. When scan chains break, it does not necessarily render them useless. Normally, scan chains can be debugged and diagnosed so that they can be fixed or used while masking out vector bits associated with broken or corrupted portions of the chain. This article describes the different ways that scan chains can break and how it tends to affect their performance. It explains how to repair various types of scan chain failures or at least regain partial use for limited testing purposes.

This article is the third in a multi-part series describing techniques for thinning and polishing a highly warped die. Tighter thickness tolerance and thinner samples are always desired. The first article addressed global thinning of a sample. The second focused on the process and problems of thinning only the area of interest. This installment covers processes and considerations for both global and area of interest treatment and provides reference process recipes.

This column explains what it takes to set up and run a successful foundry-based failure analysis laboratory.

Magnetic field imaging is proving to be a valuable tool for semiconductor failure analysts and test engineers. One of its main advantages is that it does not require sample preparation or deprocessing because magnetic fields pass through most materials used in ICs and device packages. This article discusses the theory and practical limitations of magnetic field imaging and demonstrates its use in mapping current density and determining the location and depth of current-carrying conductors.