Search Results for electronic device packaging

It seems that scaling of chip technology according to Moore’s Law will continue for digital functionalities (logic and memory); however, increasing system integration on chip and package levels, called “More than Moore,” has been observed in the past several years. This strong trend in the worldwide semiconductor industry enables more functionality, diversification, and higher value by creating smart microsystems. This article discusses the many challenges faced in FA of 3-D chips, where well-staffed and equipped FA labs are essential. Furthermore, FA is becoming an important strategic enabling factor for new products, not just another “cost factor.”

Failure analysis is becoming increasingly difficult with the emergence of 3D integrated packages due to their complex layouts, diverse materials, shrinking dimensions, and tight fits. This article demonstrates several FA techniques, including high-frequency scanning acoustic microscopy, lock-in thermography, and FIB cross-sectioning in combination with plasma ion etching or laser ablation. Detailed case studies show how the various methods can be used to analyze bonding integrity between different materials, chip-to-chip interface structures, buried interconnect defects, and through-silicon vias at either the device or package level.

Chip-scale packages (CSPs) make efficient use of space on PCBs, but their small size, multilevel stacking arrangements, and complex interconnects present serious challenges when it comes to testing and failure analysis. This article describes some of the problems encountered when dealing with various types of CSPs and provides practical solutions based on the tools and techniques available in most FA labs. It discusses the causes and effects of package and die related failures and walks readers through the steps involved in decapsulating plastic FBGA packages using conventional etching, polishing, and milling techniques.

Time domain reflectometry (TDR) is widely used to measure the electrical length of conductors. It has also proven useful for isolating failures in ICs. This article describes a variation of the method, called comparative TDR, that overcomes inherent timing limitations and simplifies use. It discusses the basic hardware requirements of the new technique and presents examples demonstrating its use on opens and shorts in ceramic flip-chip packages.

This article discusses the concept of a virtual known good device (VKGD) and how it used in the development of advanced 3D packaging. It explains that a VKGD is essentially an electromagnetic model of an IC package, including bumps, interposers, and through-silicon vias. These models, used in conjunction with reflectometry data, help engineers isolate faults in the early stages of IC package development, greatly reducing cycle times.

This is the concluding portion of a two-part article on counterfeit ICs. The first part, published in the November 2008 issue of EDFA , discussed the rise of counterfeit ICs and some of the techniques used to identify them. Part II describes a process for device authentication, from material procurement to laboratory analysis, and provides examples of its use. It also discusses ongoing efforts to remove counterfeit ICs from the supply chain.

The Package Innovation Roadmap Council (PIRC) was established as part of the Failure Analysis Technology Roadmap activity at the direction of the EDFAS Board. This column provides an overview of a technical paper by the PIRC that highlights recent innovations, technology gaps, and future development trends in package fault isolation and failure analysis. The paper focuses on three main categories: 1) Artificial intelligence (AI) applications, 2) Sample handling, and 3) FA tool robustness.

With the July 2006 implementation of RoHS (the restriction of the use of certain hazardous substances in electrical and electronic equipment), the electronics reliability industry has seen a changeover to lead-free solders and “green” mold compounds that have no bromine- or antimony-based flame retardants. This article addresses some of the challenges caused by implementation of the new requirements.

The inverted orientation of a flip-chip packaged die makes it vulnerable to optical attacks from the backside. This article discusses the nature of that vulnerability, assesses the threats posed by optical inspection tools and techniques, and provides insights on effective countermeasures.

The Assembly Analytical Forum (AAF) is an organization under the auspices of the Sematech Quality Council. The AAF charter is to develop Packaging Analytical Roadmaps five to ten years into the future that are consistent with the International Technology Roadmap for semiconductors (ITRS). At ISTFA 2003, the AAF will convene with interested conference attendees to review, edit, and validate a white paper that will quantify critical gaps in the current suite of test, measurement, and characterization tools used in the semiconductor industry and provide recommendations on how to address them. The intent is to update the document biannually and review it in numerous industry venues to ensure its relevancy and utility. This article is somewhat of a preview to the Rev 0 AAF white paper.

The U.S. CHIPS and Science Act includes $52 billion in subsidies for domestic semiconductor research and manufacturing. This guest editorial describes the program's scope and potential impact on the microelectronics industry.

The complexity of sample preparation and deprocessing has risen exponentially with the emergence of 2.5-D and 3D packages. This article provides answers and insights on how to deal with the challenges of increasingly complex semiconductor packages. After identifying pressing issues and potential bottlenecks with state-of-the-art FA flows, the authors present two case studies demonstrating the capabilities of electro-optical terahertz pulse reflectometry (EOTPR), plasma FIB milling, and 3D X-ray imaging. The FA results confirm the potential of all three techniques and indicate that a fully nondestructive integration flow for 3D packages may be achievable with further development and optimization.

This column explains how simulation tools and materials life data can provide a new level of productivity for engineers involved in forensic analysis of MEMS devices.

Electro optical terahertz pulse reflectometry (EOTPR) is a nondestructive fault isolation technique that is well suited for today’s ICs. This article provides examples of how EOTPR is being used to investigate 2.5D and 3D packages, wafer level fanout packages, and MEMS devices. It also discusses recent advancements in EOTPR systems and software.

Chip-scale packages (CSPs) make efficient use of space on PCBs, but their small size, multilevel stacking arrangements, and complex interconnects present serious challenges when it comes to testing and failure analysis. This article describes some of the problems encountered when dealing with various types of CSPs and provides practical solutions based on the tools and techniques available in most FA labs. It discusses the causes and effects of package and die related failures and walks readers through the steps involved in decapsulating plastic FBGA packages using conventional etching, polishing, and milling techniques. It also includes a case study involving a failure caused by improper laser marking.

Although plastic-encapsulated packaging dominates most of the IC industry, deprocessing and reliability testing continue to be a problem, particularly in industries making the switch from hermetically sealed ceramic packages. This article discusses the challenges designers and failure analysts face in the military and aerospace electronics industry stemming from the use of plastic packages. It provides examples of the types of failures encountered and describes the procedures used to detect and identify them.

This article provides an overview of a commercial 3D X-ray system, explaining how it acquires high-resolution images of submicron defects in large intact samples. It presents examples in which the system is used to reveal cracks in thin redistribution layers, voids in organic substrates, and variations in TSV metallization on 300-mm wafers. As the authors explain, each scan can be done in as little as a few minutes regardless of sample size, and the resulting images are clear of the beam hardening artifacts that often cause problems in failure analysis and reverse engineering.

This article describes the physical characteristics, operating principles, and key failure modes of light-emitting diodes (LEDs), focusing on phosphor-converted blue LEDs because of their relative importance. The explanations throughout the article are supported by graphics that reveal microscale features of interest as well as defects.

Several failure analysis case studies have been conducted over the past few years, illustrating the importance of preserving root-cause evidence by means of artifact-free decapsulation. The findings from three of those studies are presented in this article. In one case, the root cause of failure is chlorine contamination. In another, it is a combination of corrosion and metal migration. The third case involves an EOS failure, the evidence of which was hidden under a layer of carbonized mold compound. In addition to case studies, the article also includes images that compare the results of different decapsulation methods.

Integrated circuits are subjected to various forms of friction during fabrication and packaging, creating potential problems due to the buildup of charge. This article looks at the distinct characteristics of triboelectric charging damage on silicon-on-insulator devices at the wafer and package level. Telltale signs of this type of damage include spatial dependency, distinct TIVA-signal patterns, and bimodal static current distributions with significant changes after burn-in.