With the introduction of 65 nm technology, the cross-sectional dimensions of copper interconnect in some layers are now smaller than 100 nm, which translates to current densities on the order of several MA/cm2. Electromigration as a root cause for chip failure is thus a major concern and is still being examined. In this article, the authors present recent failure analysis studies on metal-coated copper interconnects, using OBIRCH techniques in combination with FIB cross-sectioning and SEM and TEM imaging.

Electromigration is a wearout mechanism that contributes significantly to IC failures. This article discusses the causes and effects of this often overlooked failure mode and presents practical guidelines to help analysts determine whether or not electromigration is the cause of a particular failure. It also discusses the differences between aluminum and copper electromigration.

Resistive interconnections, a type of soft failure, are extremely difficult to find using existing backside methods, and with flip-chip packages, alternative front side approaches are of little or no help. In an effort to address this challenge, a team of engineers developed a new method that uses the effects of resistive heating to directly locate defective vias, contacts, and conductors from either side of the die. In this article, they discuss the basic principles of their new method and demonstrate its use on two ICs in which a variety of resistive interconnection failures were found.

This article describes an automated sample preparation process for SEM and TEM analysis based on submicron polishing. The method uses robotics, image processing, and a polishing wheel under computer control for a fully automated recipe-driven process that creates exact cross-sections with 0.1 μm accuracy.

This article describes the basic measurement physics of scanning nitrogen vacancy (NV) microscopy and the various ways it can be used in semiconductor device failure analysis. Scanning NV microscopy can measure topography as well as magnetic fields, local current density, ac noise, and local temperature variations.

Stress voiding has re-emerged as a concern in advanced metal systems with their reduced dimensions and multilayer designs. Unless analysts are familiar with the physics and history of stress voids in ICs, chances are they will go unnoticed. This article discusses the basic cause of stress cracks and the clues that give them away.

Parametric failures are of two general types. One type is due to defects that affect circuit parameters. The other type, which occurs in defect-free parts, is the result of interdie parameter statistical variation. IC failures can be caused by variations in any number of parameters including L eff , W eff , I Dsat , V t , contact resistance, effective gate oxide thickness, source and drain resistance, interconnect sheet resistance, and intrametal spacing affecting cross-talk, ground bounce noise, and IR voltage drops. These failures often influence the maximum operating frequency of the IC and are seldom detected by simple stuck-at fault, delay fault, functional, or I DDQ tests. This article discusses the origin, classification, and detection of a wide range of parametric failures.

This article reviews key events from past International Symposium for Testing and Failure Analysis events, held in 1975, 1985, and 1995.

Unit level traceability (ULT) is a powerful tool that allows complete die histories to be accessed in the course of testing and analysis. It is especially useful for identifying the likely causes of microprocessor failures and in cases where failure analysis resources are limited. In the article, the author explains how he used ULT in the investigation of a 0.25-µm CMOS processor. Using the ULT of the die, he discovered a failure signature based on die location on the wafer. One root cause of failure was traced to cross-field variation in the lithography process due to marginal focus control. Another failure, observed after burn-in, was traced to the presence of residual titanium left after metal etch.

A detailed analysis based on FIB etching and SEM image capture was conducted on a flip-chip solder joint deep inside a tablet PC. 3D views reconstructed from SEM images show what appears to be a copper pillar with a solder cap connected to a copper trace on the substrate. The investigators believe the joint was formed by thermal compression bonding with a preapplied underfill. The analysis also revealed the presence of voids and intermetallic compounds along with signs of filler entrapment.

This article proposes the MicroStructural Hierarchy Descriptor (µSHD) as a systematic and quantitative approach to spectra and image data in microelectronics failure analysis. It discusses concrete routes for employing µSHD directly as the quantitative descriptor for supervised and unsupervised machine learning. The authors propose that µSHD tools can be used to automate and improve characterization techniques and image processing and analysis protocols.

The Assembly Analytical Forum (AAF) is an organization under the auspices of the Sematech Quality Council. The AAF charter is to develop Packaging Analytical Roadmaps five to ten years into the future that are consistent with the International Technology Roadmap for semiconductors (ITRS). At ISTFA 2003, the AAF will convene with interested conference attendees to review, edit, and validate a white paper that will quantify critical gaps in the current suite of test, measurement, and characterization tools used in the semiconductor industry and provide recommendations on how to address them. The intent is to update the document biannually and review it in numerous industry venues to ensure its relevancy and utility. This article is somewhat of a preview to the Rev 0 AAF white paper.

This article discusses the latest trends in wire bonding and examines common failure mechanisms.

Scanning probe microscopy (SPM) refers to a suite of techniques that measure the interaction between a fine probe or tip and a sample in contact or close proximity. These interaction measurements allow the study of properties such as topology, magnetic and electric fields, capacitance, temperature, work function, and friction. The information obtained from SPM plays an important role in IC failure analysis.

Stress voiding is an insidious IC failure mechanism that can be difficult to identify and arrest. It is of particular concern to those who produce and test ICs with aluminum-alloy interconnects or who assess the reliability of legacy devices with long service life. This article explains how stress voids form and grow and how to determine the root cause by amassing physical evidence and ruling out other failure mechanisms. The key to differentiating stress voiding from other types of failures is recognizing that is the result of three distinct physical phenomena, stress, nucleation, and diffusion, all of which must be confirmed before attempting to make process corrections.

CMOS IC failure mechanisms are of three general types: bridge defects, open circuit defects, and parametric related failures. This article summarizes bridge and open-circuit defect properties and provides references for further self-study. Bridge defects are characterized based on location, their significance in terms of logic gates and transistors, and critical resistance for dc logic and timing failures. Open defects are more complex and diverse with six possible failure modes each of which are described in the article.

Transmission electron microscopes have been improved in various ways over the past two decades, giving rise to new characterization techniques. Among the innovations discussed in this article are the introduction of field emission guns, the incorporation of CCD cameras and X-ray detectors, and the use of lens correction systems. Such improvements have had a significant impact on failure analysis through the emergence of new TEM techniques, including precession electron diffraction for grain and strain analysis, noise reduction processing for low dose EELS mapping of ultra-low-k materials, and EDX tomography for elemental 3D imaging of defects on a nanometer scale.

The use of a pulsed laser with a lock-in amplifier has been shown to increase the detection sensitivity of scanning optical microscopes by a factor of ten. In this article, the authors explain how they implement laser pulsing without a lock-in amplifier through software control. The detection sensitivity of their method, which is based on a digital signal integration algorithm, has been shown to be comparable to that achieved with a lock-in amplifier. Several case studies illustrate the effectiveness of the technique for locating various types of defects.

This article discusses the causes and effects of stuck-open faults (SOFs) in nanometer CMOS ICs. It addresses detection and localization challenges and explains how resistive contacts and vias and the use of damascene-copper processes contribute to the problem. It also discusses layout techniques that reduce the likelihood of SOF failures.

By providing timing information and throughput as device complexities and operating frequencies were rapidly increasing, the e-beam prober, which integrated CAD navigation and waveform measurements while enabling the user to almost disregard the technology “under the hood,” was the required tool for IC design debug from the late 1980s to the early 2000s. The history, successes, innovations, mistakes, and possible future of this workhorse tool are visited and described.