1-20 of 138 Search Results for

electrically active defects

Follow your search
Access your saved searches in your account

Would you like to receive an alert when new items match your search?
Close Modal
Sort by
Journal Articles
Publisher: Journals Gateway
EDFA Technical Articles (2002) 4 (4): 29–33.
Published: 01 November 2002
...Kristin Lee Bunker; Terry J. Stark; Dale Batchelor; Juan Carlos Gonzalez; Phillip E. Russell STEM-EBIC imaging, a nano-characterization technique, has been used in the study of electrically active defects, minority carrier diffusion length, surface recombination velocity, and inhomogeneities in Si...
Journal Articles
Publisher: Journals Gateway
EDFA Technical Articles (2012) 14 (4): 4–11.
Published: 01 November 2012
... electrically active defects are not directly observable by conventional techniques. However, their effects can be so detrimental for devices such as complementary metal-oxide semiconductor (CMOS) image sensors that their fingerprints can be obtained. In particular, dark current monitoring applied...
Journal Articles
Publisher: Journals Gateway
EDFA Technical Articles (2001) 3 (4): 29–35.
Published: 01 November 2001
... International defect localization electrically active defects OBIC analysis single contact optical beam induced currents httpsdoi.org/10.31399/asm.edfa.2001-4.p029 EDFAAO (2001) 4:29-35 ©ASM International Single Contact Optical Beam Induced Currents (SCOBIC) Technique and Applications Best Paper...
Journal Articles
Publisher: Journals Gateway
EDFA Technical Articles (2016) 18 (1): 4–12.
Published: 01 February 2016
... complementary advanced techniques have been combined to highlight these unusual silicon crystal defects. Starting with electrical investigations, the electrical impact of those latent defects causes parametric or functional failures. Then, fault localization techniques such as infrared, emission microscopy...
Journal Articles
Publisher: Journals Gateway
EDFA Technical Articles (2012) 14 (4): 12–18.
Published: 01 November 2012
... and test results is the first step to a successful physical failure analysis of the provoking defects. Electrical measurements are performed with DRAM internal circuits and external time control by the DRAM command interface. For the next step, activation is used as an example to discuss the data...
Journal Articles
Publisher: Journals Gateway
EDFA Technical Articles (2003) 5 (4): 27–32.
Published: 01 November 2003
... for dislocation generation, then the device will eventually fail. Many optoelectronic materials have a problem wherein the dislocations grow toward the area with optical activity; that is, they will seek and find the active region. Once they reach the active region, dark line defects and dark spot defects form...
Journal Articles
Publisher: Journals Gateway
EDFA Technical Articles (2015) 17 (3): 4–10.
Published: 01 August 2015
... of these properties in one process. As a surface electrical failure analysis technique, nanoprobing can be performed on either a single interconnect layer or a sequence of multiple interconnect layers, with delayering steps in between. If front-end devices are suspected and back-end metal defects can be ruled out...
Journal Articles
Publisher: Journals Gateway
EDFA Technical Articles (2018) 20 (3): 24–33.
Published: 01 August 2018
...: LOCATING RESISTOR CHAIN DEFECTS The device under test (DUT) in this case consisted of a continuous contact chain between silicided N-active islands and the metal 1 layer manufactured in 28 nm technology. In the first case, this chain exhibited a high ohmic link failure that was found during in-fab...
Journal Articles
Publisher: Journals Gateway
EDFA Technical Articles (2006) 8 (3): 12–17.
Published: 01 August 2006
... it is activated. Figure 1 shows a 2-NAND gate accompanied by a truth table response for inputs AB and output C that has an open-circuit defect in the source of p-MOS transistor B. Notice in the table that despite a large open defect, the logic gate responds correctly to the ordered truth table inputs. How can...
Journal Articles
Publisher: Journals Gateway
EDFA Technical Articles (2000) 2 (4): 25–30.
Published: 01 November 2000
... to the substrate. The I-V curves show typical active-towell diode characteristics. Therefore, the possibility that either of these contacts is highly resistive or open was ruled out. Overall, electrical isolation narrowed the defect down to either the polysilicon gate or the active regions of a single n-channel...
Journal Articles
Publisher: Journals Gateway
EDFA Technical Articles (2013) 15 (3): 4–11.
Published: 01 August 2013
... stimulus to provide greater capabilities. This example illustrates the use of LIT on a scan chain failure.[5] A custom electrical test with related synchronization was developed for the failure, as illustrated in Fig. 3. The pattern was set to activate the failure in the first half of the test pattern...
Journal Articles
Publisher: Journals Gateway
EDFA Technical Articles (2020) 22 (2): 29–35.
Published: 01 May 2020
... and axial resolution for 3D measurements. This article describes an approach for 3D-localization of thermally active defects by lock-in thermography. It is based on the technique's superior sensitivity of LIT signals to temporal variations with respect to the electrical stimulation. In this approach...
Journal Articles
Publisher: Journals Gateway
EDFA Technical Articles (2020) 22 (4): 10–16.
Published: 01 November 2020
... vary as a function of depth through the film. SIMS provides chemical composition profile data which can only be translated into electrical property information in cases where all the dopants are fully activated in the layer. This is clearly not the case in advanced device structures where, for example...
Journal Articles
Publisher: Journals Gateway
EDFA Technical Articles (2002) 4 (1): 12–16.
Published: 01 February 2002
... to receive mode. A bad chip took tens of nanoseconds to get the right value. This can also be formulated as a slow-to-disable problem. Figure 1 shows the electrical measurements on good and bad I/O. The problem was suspected to be a random defect in a widely used I/O circuit. Locating the defect by contact...
Journal Articles
Publisher: Journals Gateway
EDFA Technical Articles (2006) 8 (1): 6–14.
Published: 01 February 2006
...Martin Versen; Achim Schramm; Florian Schamberger; Ingo Klein This article demonstrates the strengths and limitations of electrical testing for locating defects that contribute to contact failures in DRAMs. It presents three case studies, the first of which involves a write problem to a pair...
Journal Articles
Publisher: Journals Gateway
EDFA Technical Articles (2018) 20 (1): 10–18.
Published: 01 February 2018
... analysis localization because of its dynamic failure mode with a test sequence that is hard to set up. It does not show abnormality in parametric measurements when probing isolated transistors, because of its transient electrical activation. Finally, it does not show visible and morphological defects...
Journal Articles
Publisher: Journals Gateway
EDFA Technical Articles (2016) 18 (3): 10–16.
Published: 01 August 2016
...S.H. Goh; B.L. Yeoh; G.F. You; Y.H. Chan; Zhao Lin; Jeffrey Lam; C.M. Chua This article explains how hardware and software enhancements bring new capabilities to one of the most widely used soft-defect localization techniques. It discusses the basic concept of electrically enhanced laser-assisted...
Journal Articles
Publisher: Journals Gateway
EDFA Technical Articles (2011) 13 (3): 12–16.
Published: 01 August 2011
...Roger Nicholson; Ted Lundquist Laser voltage imaging (LVI) enables the global visualization of on-chip circuit activity for the purpose of localizing defects. In a manner reminiscent of e-beam voltage contrast, it allows analysts to visually trace signals through circuit logic in order to see where...
Journal Articles
Publisher: Journals Gateway
EDFA Technical Articles (2020) 22 (2): 22–28.
Published: 01 May 2020
... SRAM after standard FIB cross-section imaging failed to reveal any visible defects. Scanning capacitance microscopy (SCM) and nanoprobing are key tools for isolating and understanding transistor level fails. In this case study, SCM and nanoprobing are used to determine the electrical...
Journal Articles
Publisher: Journals Gateway
EDFA Technical Articles (2010) 12 (4): 22–27.
Published: 01 November 2010
...[8] are some examples of methodologies. Laser Stimulation for IC Failure Analysis In this technique, the laser beam is focused and scanned over the active region of the device under test (DUT). Laser stimulation is used to locally perturb the electrical properties of the DUT, and the changes...