STEM-EBIC imaging, a nano-characterization technique, has been used in the study of electrically active defects, minority carrier diffusion length, surface recombination velocity, and inhomogeneities in Si pn junctions. In this article, the authors explain how they developed and built a STEM-EBIC system, which they then used to determine the junction location of an InGaN quantum well LED. They also developed a novel FIB-based sample preparation method and a custom sample holder, facilitating the simultaneous collection of Z-contrast, EBIC, and energy dispersive spectroscopy images. The relative position of the pn junction with respect to the quantum well was found to be 19 ± 3 nm from the center of well.

This article discusses the basic principles of dark current spectroscopy (DCS), a measurement technique that can detect and identify low levels of metal contaminants in CMOS image sensors. An example is given in which DCS is used to determine the concentration of tungsten and gold contaminants in an image sensor and estimate the dark current generated by a single atom of each metal.

Single contact optical beam induced currents (SCOBIC) is a variation on the OBIC failure analysis technique that requires only one point of contact with the junction being examined. This article discusses the basic principles of this new method and how it compares with OBIC in terms of measurement performance. It also presents examples showing how SCOBIC can be used to analyze CMOS devices from the front and back side without need for complex FIB and microprobing procedures.

Silicon pipeline defects are a growing concern in semiconductor manufacturing with no proposed methodology on how to effectively analyze them and separate the underlying causes. In light of this need, a study was conducted using complementary FA techniques to examine these unusual silicon crystal defects and gain a better understanding of their signature characteristics and their effect on device failure. This article, authored by the lead investigator, describes the tests that were performed and presents relevant findings and theories on the factors that contribute to "pipeline" and how they can be controlled. It also presents guidelines for distinguishing between pipeline and dislocation defects and explains how they are related.

This article discusses the types of defects that occur in vertical cavity surface-emitting lasers (VCSELs) and the tools typically used to detect them and identify the cause. It describes the basic design and operation of VCSELs and explains that most failures are due to dislocations in the crystal structure of the materials from which the devices are made. Of the various methods used to analyze such defects, electroluminescence (EL) is by far the most powerful as demonstrated in several EL images included in the article. The article also discusses the use of EBIC analysis, FIB cross-sectioning, and thermally induced voltage alteration (TIVA).

Failure analysis of dynamic random access memory follows a three-step process consisting of electrical test and diagnosis, localization, and physical defect analysis. The electrical test delivers pass-fail results that are graphically displayed in bitmaps, which are then used to localize defects based on layout data. This article describes each step of the process and compares and contrasts laser scanning techniques.

Advances in IC technology have made failure site localization extremely challenging. Through a series of case studies, the authors of this article show how such challenges can be overcome using EBIC/EBAC, current imaging, and nanoprobing. The cases involve a wide range of issues, including resistor chain defects, substrate leakage, microcracking, micro contamination, and open failures due to copper plating problems and missing vias.

This article discusses the causes and effects of stuck-open faults (SOFs) in nanometer CMOS ICs. It addresses detection and localization challenges and explains how resistive contacts and vias and the use of damascene-copper processes contribute to the problem. It also discusses layout techniques that reduce the likelihood of SOF failures.

IDDQ testing is normally the key to isolating state-dependent defects in dense ICs. In the case study presented here, however, the functionally failing ICs did not fail the static IDDQ test nor did they draw significant current when biased into a static state on the lab bench. After extensive testing and analysis, including ATE IDDQ scanning, ATE-interfaced photo-emission microscopy, FIB assisted mechanical microprobing, and scanning capacitance microscopy, the defect was found to be p-type counterdoping of the n-active regions caused by a contaminated solvent tank used during wafer fabrication.

Atomic force microscopy has been a consistent factor in the advancements of the past decade in IC nanoprobing and failure analysis. Over that time, many new atomic force measurement techniques have been adopted by the IC analysis community, including scanning conductance, scanning capacitance, pulsed current-voltage, and capacitance-voltage spectroscopy. More recently, two new techniques have emerged: diamond probe milling and electrostatic force microscopy (EFM). As the authors of the article explain, diamond probe milling using an atomic force microscope is a promising new method for in situ, localized, precision delayering of ICs, while active EFM is a nondestructive alternative to EBAC microscopy for localization of opens in IC analysis.

The shrinking geometries in today’s 3-D integrated circuit (IC) designs generate an urgent need for a variety of tools to isolate failures on advanced semiconductor devices. There has been no single technique that adequately addresses all types of failures with the required fast cycle time. Complex failures that are not resolved by the faster global approaches are best addressed by probing technologies, where waveforms or voltages are measured from node to node. These approaches are time-consuming and usually require detailed understanding of the circuit operation. Global techniques that map the secondary effects of defects have been widely used for as many failures as possible. These secondary effects include thermal emission, photon emission, and circuit operation dependencies on localized heating or carrier generation at a defect site. Each technique addresses some segment of the failure mechanisms, but none is universally effective in itself. The use of thermal emission techniques has waned due to the issues of lower power supply voltages, which result in poor sensitivity for older techniques and decrease in minimum resolved feature sizes.

Picosecond imaging circuit analysis (PICA) is an advanced diagnostic technique that measures device switching activity on CMOS ICs through the backside of the die. Due to its relatively large field of view, it can quickly locate defects among large numbers of candidates. In this case study, the authors explain how they used PICA to identify a particular I/O circuit defect on the IBM System/390 G5 microprocessor. They also explain how they verified the diagnostic result using circuit simulations.

This article demonstrates the strengths and limitations of electrical testing for locating defects that contribute to contact failures in DRAMs. It presents three case studies, the first of which involves a write problem to a pair of cells that share an open bitline contact. The second case, a read problem between the primary and secondary sense amplifiers, serves as an example of how failure bitmaps and electrical characterization work together to detect and locate defects. The third case is a decoder problem that required additional testing and internal probing in order to determine the location of the defect.

This article describes a form of lock-in thermography that achieves 3D localization of thermally active defects in stacked die packages. In this approach, phase shifts associated with thermal propagation delay are analyzed as a function of frequency. This allows for a precise localization of defects in all three spatial dimensions and can serve as a guide for subsequent high-resolution physical analyses.

Scanning capacitance microscopy (SCM) and nanoprobing are key tools for isolating and understanding transistor level fails. In this case study, SCM and nanoprobing are used to determine the electrical characteristics of cluster-type failures in 14 nm SOI FinFET SRAM after standard FIB cross-section imaging failed to reveal any visible defects.

Laser voltage imaging (LVI) enables the global visualization of on-chip circuit activity for the purpose of localizing defects. In a manner reminiscent of e-beam voltage contrast, it allows analysts to visually trace signals through circuit logic in order to see where faults occur. This article explains how laser voltage imaging works and how it is being used in semiconductor failure analysis. It also describes the types of applications for which LVI is not well suited.

Soft electrical failures caused by monograin defects can have a significant impact on yield in technology nodes below 40 nm. Moreover, the failures are hard to identify and the defects give very few signatures during localization testing. In this article, the authors explain how they used nanobeam diffraction with automated crystal orientation and phase mapping to pinpoint a single grain orientation causing the problem and, as a result, are now able to recognize the symptoms of this type of failure, observe the defect, and limit the impact on electrical timing margins through both design and process corrections.

This article explains how hardware and software enhancements bring new capabilities to one of the most widely used soft-defect localization techniques. It discusses the basic concept of electrically enhanced laser-assisted device alteration (EeLADA) and demonstrates its use on different types of soft and hard defects. It also discusses the relative advantages of hardware and software implementations.

Differential Hall effect metrology (DHEM) provides depth profiles of all critical electrical parameters through semiconductor layers at nanometer-level depth resolution. This article describes the relatively new method and shows how it is used to measure mobility and carrier concentration profiles in different materials and structures.

Scanning probe microscopy (SPM) is widely used for fault isolation as well as diagnosing leakage current, detecting open circuits, and characterizing doping related defects. In this article, the author presents two SPM applications that are fairly uncommon but no less important in the scope of failure analysis. The first case involves the discovery of nano-steps on the surface of high-voltage NFETs, a phenomenon associated with stress-induced crystalline shift along the (111) silicon plane. In the second case, the author uses an AFM probe in the conductive mode to correlate tunneling current distribution with hot spots in high-k gate oxide films, which is shown to be a better indicator of oxide quality than rms surface roughness.