Search Results for electrical inspection

Scanning laser-SQUID microscopy is a new electrical inspection and failure analysis technique that can detect open, high-resistance, and shorted interconnects without electrical contact in areas ranging in size from a few square microns to an entire die. This article describes the setup of a prototype laser-SQUID system, explaining how it works and how it compares to other nondestructive defect localization techniques. It presents application examples in which laser-SQUID microscopy is used to locate gate oxide shorts to within 1.3 μm and detect IC defects prior to bond-pad pattering and after bonding and packaging. It also includes a series of images acquired from a board-mounted chip with fields of view ranging from 5 x 5 mm down to 50 x 50 μm.

Counterfeit electronic parts have become a significant cause of concern in the electronics part supply chain. Several factors that contribute to the targeting of the electrical, electronic, and electromechanical (EEE) parts market by counterfeiters include parts obsolescence, extended lead times, the absence of verification tools, the availability of scrapped or salvaged parts, and the high costs associated with inspection/testing procedures. This article reports on the status of efforts by the G-19 Committee of SAE International to develop standards in response to increasing numbers of counterfeit parts in the supply chain.

Electronic device failure analysis usually starts with electrical testing, followed by visual inspection via optical microscopy, then examination in a scanning electron microscope. When imaging reveals the need to determine the composition of materials, defects, and suspected contaminants, the electron beam produced by the SEM can be used to obtain the necessary information. As the article explains, this is the basic concept behind the method known as energy dispersive X-ray spectroscopy (EDS or EDX) and the key to its widespread use. In addition, the article presents three examples showing how SEM/EDS measurements helped failure analysts identify human contaminants on a die sample, determine the source of a particle embedded in the film stack on a wafer, and conclude that lead spatter from a solder die-attach preform caused wire bond lift.

Passive voltage contrast (PVC) has traditionally been used by semiconductor engineers for end-of-line post-mortem analysis. PVC distinguishes between open and short structures and is both nondestructive and noncontact. When applied during process development for in-line characterization, it allows wafers to be examined at multiple points, where electrical probing might not be feasible. This provides feedback on the cumulative effect of the process on critical parameters such as oxide integrity and can reduce development cycle times because wafers do not have to be deprocessed in order to determine the exact location of failures. Two case studies are presented in this article, demonstrating the use of PVC in a process development environment.

Scan-based diagnostics produce high-confidence target lists of suspected faults associated with electrical fail signatures. Physical coordinates extracted from these lists serve as a guide for physical failure analysis. When certain conditions are met for the design database and pattern sets, the extraction can be automated and the analysis completed within minutes. The logic mapping flow is a natural extension of scan-based diagnosis with the potential to reach new levels of electrical failure analysis without the extensive data collection and resources associated with signature analysis. This article describes the logic mapping concept and how to implement the flow. It also presents the results of actual cases in which logic mapping was used.

This article presents a comprehensive study of physical inspection and attack methods, describing the approaches typically used by counterfeiters and adversaries as well as the risks and threats created. It also explains how physical inspection methods can serve as trust verification tools and provides practical guidelines for making hardware more secure.

This article is the first in a two-part series analyzing solder connection failures between BGA packages and PCB assemblies. Part I examines failures attributed to oxygen intrusion during reflow, underetched solder resist, and solder paste printing problems. In the latter case, X-ray inspection revealed no abnormalities other than a variation in ball size. To get to the root cause, the corpus of the BGA was progressively ground away, leaving only the balls and an unobstructed view of the PCB surface. A description of the process, supported by detailed images, is included in the article. In Part II, scheduled for the May 2017 issue of EDFA, the author delves deeper into the analysis of voids and presents an alternate FA approach that involves grinding away much of the PCB.

The Product Analysis Forum (PAF), sponsored by the Quality Council of SEMATECH, has been chartered to facilitate the ongoing development of tools and techniques for semiconductor characterization and failure analysis. Drawing on input from industry experts, universities, and national laboratories, the PAF has identified critical needs in three areas: software fault isolation, backside fault isolation, and deprocessing & inspection. This article discusses the current state of deprocessing and inspection technology and provides insights into how some of the future challenges will be addressed.

A review of the 2001 edition of the International Technology Roadmap for Semiconductors indicates major obstacles ahead. Of the three basic failure analysis steps—inspection, deprocessing, and fault isolation—the latter is the most at risk, especially physical fault isolation.

This article explains how the failure of a high-voltage capacitor led to the discovery of an unusual defect. Testing showed that the capacitor shorted due to silver migration, which investigators believe was facilitated by voids in the dielectric that had been present from the time of manufacture. Through some combination of time, electric potential, trapped humidity, and elevated operating temperature, plate material migrated into the voids, creating a short path that led to the failure. Using acoustic images as a guide, the failed capacitor was cross-sectioned, allowing investigators to examine the voids more closely and thereby confirm their theory.

This article describes a proposed novel metric to furnish chip designers with a prognostic tool for x-ray imaging in the pre-silicon stage. This metric is fashioned to provide designers with a concrete measure of how visible the fine-pitched features of their designs are under x-ray inspection. It utilizes a combination of x-ray image data collection, analysis, and simulations to evaluate different design elements.

Engineers at the Fraunhofer Institute for Microstructure of Materials and Systems built and are testing a scanning acoustic microscope (SAM) that operates at frequencies of up to 2 GHz. Here they describe the design of their GHz-SAM and present examples showing how it is used to detect stress induced voids, inspect wire bond interfaces, and examine through-silicon vias (TSVs) in the time-resolved mode.

This column reports on efforts by the SAE G-19A committee to develop an aerospace industry standard on practices to detect suspect counterfeit components, maximize the use of authentic parts, and ensure consistency across the supply chain for test techniques and requirements.

Interposers play an important role in 2.5D and 3D packages, routing power and communication signals between dies while maintaining electrical contact with I/O pins. This role and their relatively simple construction makes interposers a target for malicious attacks. In this article, the authors assess the vulnerabilities inherent in the fabrication of interposers and describe various types of optical attacks along with practical countermeasures.

Scanning acoustic tomography (SAT) is widely used to detect defects such as voids and delamination in electronic devices. In this article, the authors explain how they improved the spatial resolution and detection sensitivity of SAT by switching from a conventional piezoelectric probe to a capacitive micromachined ultrasound transducer (CMUT) and by using pulse compression signal processing. They also present examples showing how the improvement makes it possible to detect very small defects in multilayer stacks and BGA packages whether in through-transmission or reflection imaging mode.

This is the concluding portion of a two-part article on counterfeit ICs. The first part, published in the November 2008 issue of EDFA , discussed the rise of counterfeit ICs and some of the techniques used to identify them. Part II describes a process for device authentication, from material procurement to laboratory analysis, and provides examples of its use. It also discusses ongoing efforts to remove counterfeit ICs from the supply chain.

Integrated circuits embedded in everyday devices face an increased risk of tampering and intrusion. In this article, the authors explain how reverse engineering techniques, including automated image analysis, can be employed to provide trust and assurance when dealing with commercial off-the-shelf chips.

This article presents best practices and procedures for analyzing printed circuit board assembly failures. It discusses the role of electrostatic discharge and electrical overstress, the increasing complexity of ball grid arrays and buried vias, the challenges associated with lead-free solder processes, and the problems caused by counterfeit components flowing into our supply lines. It also includes a summary of the tools available to failure analysts and how they are best put to use

The semiconductor industry has followed Moore’s law in the last four decades. However, transistor performance improvement will be limited, and designers will not see doubling of frequency every two years. The need for increased performance and further miniaturization has driven the development of advanced packaging solutions, such as fan-in wafer-level chip-scale packaging, fan-out wafer-level packaging, wire-bonded stacked dice, and package-on-package. These technologies are used in mass production and provide significant benefits in form factor but may not give the desired improvement in die-to-die bandwidth. Recently, 3-D integrated circuits (ICs) that employ vertical through-silicon vias (TSVs) for connecting each die have been proposed. It is an alternative solution to existing package-on-package and system-in-package processes. This column addresses some of the challenges in implementing new TSV techniques.

Nanoprobing of transistors and resistors is increasing in importance for both design debug and electrical fault isolation. It is thus necessary to understand the impact of scanning a resistor or transistor with an electron beam in order to draw valid conclusions from nanoprobe measurements. In this article, the authors show that exposing samples to electron beams with energies above 4 keV can change the value of diffusion resistors by as much as 30% and that changes can occur at even lower voltages in areas of the sample covered with less material. The article also sheds light on why the changes occur.