Although much traditional FA depends on physical observation to localize failures, electrical techniques are also important, particularly with advances in design for testability (DFT) on modern ICs. DFT structures combined with automated test equipment and algorithmic fault diagnosis facilitate a test-based fault localization (TBFL) approach to identify defect locations on ICs based on scan test patterns. This article and a companion piece in the November 2001 issue of EDFA provide an overview these methods and show how they can reduce the number of potential defect sites on a chip and, in some cases, identify defects that would be missed by other techniques.

Recent developments in two relatively new failure analysis techniques, Seebeck effect imaging (SEI) and thermally-induced voltage alteration (TIVA), have greatly improved their defect detection sensitivity and image acquisition times for localizing open and shorted interconnections. This article presents several examples demonstrating the enhanced capabilities of these two methods.

This article discusses the advantages of SEM-based nanoprobing and the various ways it can be used to locate defects associated with IC failures. It describes the basic measurement physics of electron beam induced current, absorbed electron, and voltage distribution contrast imaging and presents examples showing how the different methods are used to isolate low- and high-resistance sites, shorts, and opens as well as ion implantation and metal patterning defects.

A team of semiconductor engineers recently developed a new fault localization method tailored for high-resistance faults. In this article, they discuss the basic principle of the technique and explain how they validated it for various test cases.

Wafer-level failure analysis plays an important role in IC fabrication, both in process development and yield enhancement. This article outlines the general flow for wafer-level FA and explains how it differs for memory and logic products. It describes the tools and procedures used for failure mode verification, electrical analysis, fault localization, sample preparation, chemical analysis, and physical failure analysis. It also discusses the importance of implementing corrective actions and tracking the results.

The best spatial resolution that can be achieved with far-field optical fault localization techniques is around 20 times larger than the critical defect size at the 45 nm technology node. There is also a limit on the laser power that can be safely used on 45 nm devices, which further compromises fault localization precision. In this article, the authors explain how they overcome these limitations using pulsed laser-induced imaging techniques and a refractive solid immersion lens. Two case studies show how the combination of pulsed-laser scanning optical microscopy and a solid immersion lens improves localization precision and detection sensitivity.

A review of the 2001 edition of the International Technology Roadmap for Semiconductors indicates major obstacles ahead. Of the three basic failure analysis steps—inspection, deprocessing, and fault isolation—the latter is the most at risk, especially physical fault isolation.

Selecting a fault isolation technique for a particular type of SRAM logic failure requires an understanding of available methods. In this article, the authors review common fault isolation techniques and present several case studies, explaining how they determined which technique to use.

Atomic force microscopy has been a consistent factor in the advancements of the past decade in IC nanoprobing and failure analysis. Over that time, many new atomic force measurement techniques have been adopted by the IC analysis community, including scanning conductance, scanning capacitance, pulsed current-voltage, and capacitance-voltage spectroscopy. More recently, two new techniques have emerged: diamond probe milling and electrostatic force microscopy (EFM). As the authors of the article explain, diamond probe milling using an atomic force microscope is a promising new method for in situ, localized, precision delayering of ICs, while active EFM is a nondestructive alternative to EBAC microscopy for localization of opens in IC analysis.

Electro optical terahertz pulse reflectometry (EOTPR) is a nondestructive fault isolation technique that is well suited for today’s ICs. This article provides examples of how EOTPR is being used to investigate 2.5D and 3D packages, wafer level fanout packages, and MEMS devices. It also discusses recent advancements in EOTPR systems and software.

In most cases, microelectronic failure analysis is rooted in the observation of voltage, either as logic levels or as time-based waveforms. This is due largely to the ease of making such measurements. As a result, current measurement is often overlooked. This article discusses aspects of current measurement that can be used during fault localization, often providing information that cannot be obtained by other means.

This article assesses the capabilities of failure analysis techniques in the context of 65 nm CMOS ICs. It demonstrates the use of OBIRCH, voltage contrast, Seebeck effect imaging, SEM and TEM techniques, and FIB cross-sectioning on failures such as dielectric breakdown, open and resistive vias, voids, shorts, delaminations, and gate oxide defects.

Technologies relatively new to failure analysis, like time-correlated photon counting, electro-optical probing, antireflective (AR) coating, Schlieren microscopy, and superconducting quantum interference (SQUID) devices are being leveraged to create faster, more powerful tools to meet increasingly difficult challenges in failure analysis. This article reviews recent advances and research in fault isolation and circuit repair.

The use of a pulsed laser with a lock-in amplifier has been shown to increase the detection sensitivity of scanning optical microscopes by a factor of ten. In this article, the authors explain how they implement laser pulsing without a lock-in amplifier through software control. The detection sensitivity of their method, which is based on a digital signal integration algorithm, has been shown to be comparable to that achieved with a lock-in amplifier. Several case studies illustrate the effectiveness of the technique for locating various types of defects.

This column provides a ten-year retrospective on laser-based fault isolation techniques and the important role of laser signal injection microscopes.

A wide range of electrical faults are revealed through thermal laser stimulation (TLS). In principle, an electrical parameter, typically current or voltage, is monitored for changes caused by the heating effects of the laser. Most test setups are designed to limit the activity of the device in order to minimize the signal-to-noise ratio, but in some cases, the fault’s electrical footprint can only be detected when the device is stimulated in a dynamic way. This article describes the setup and implementation of various dynamic TLS methods and presents example applications demonstrating the advantages and limitations of each approach.

The inverted orientation of a flip-chip packaged die makes it vulnerable to optical attacks from the backside. This article discusses the nature of that vulnerability, assesses the threats posed by optical inspection tools and techniques, and provides insights on effective countermeasures.

Advances in IC technology have made failure site localization extremely challenging. Through a series of case studies, the authors of this article show how such challenges can be overcome using EBIC/EBAC, current imaging, and nanoprobing. The cases involve a wide range of issues, including resistor chain defects, substrate leakage, microcracking, micro contamination, and open failures due to copper plating problems and missing vias.

This article discusses the types of defects that occur in vertical cavity surface-emitting lasers (VCSELs) and the tools typically used to detect them and identify the cause. It describes the basic design and operation of VCSELs and explains that most failures are due to dislocations in the crystal structure of the materials from which the devices are made. Of the various methods used to analyze such defects, electroluminescence (EL) is by far the most powerful as demonstrated in several EL images included in the article. The article also discusses the use of EBIC analysis, FIB cross-sectioning, and thermally induced voltage alteration (TIVA).

Magnetic current imaging provides electrical fault isolation for shorts, leakage currents, resistive opens, and complete opens. In addition, it can be performed nondestructively from either side a die, wafer, packaged IC, or PCB. This article reviews the basic theory and attributes of MCI, describes the types of sensors used, and discusses general measurement procedures. It also presents application examples demonstrating recent advancements and improvements in MCI.