Scan-based diagnostics produce high-confidence target lists of suspected faults associated with electrical fail signatures. Physical coordinates extracted from these lists serve as a guide for physical failure analysis. When certain conditions are met for the design database and pattern sets, the extraction can be automated and the analysis completed within minutes. The logic mapping flow is a natural extension of scan-based diagnosis with the potential to reach new levels of electrical failure analysis without the extensive data collection and resources associated with signature analysis. This article describes the logic mapping concept and how to implement the flow. It also presents the results of actual cases in which logic mapping was used.

This article demonstrates the strengths and limitations of electrical testing for locating defects that contribute to contact failures in DRAMs. It presents three case studies, the first of which involves a write problem to a pair of cells that share an open bitline contact. The second case, a read problem between the primary and secondary sense amplifiers, serves as an example of how failure bitmaps and electrical characterization work together to detect and locate defects. The third case is a decoder problem that required additional testing and internal probing in order to determine the location of the defect.

Scanning laser-SQUID microscopy is a new electrical inspection and failure analysis technique that can detect open, high-resistance, and shorted interconnects without electrical contact in areas ranging in size from a few square microns to an entire die. This article describes the setup of a prototype laser-SQUID system, explaining how it works and how it compares to other nondestructive defect localization techniques. It presents application examples in which laser-SQUID microscopy is used to locate gate oxide shorts to within 1.3 μm and detect IC defects prior to bond-pad pattering and after bonding and packaging. It also includes a series of images acquired from a board-mounted chip with fields of view ranging from 5 x 5 mm down to 50 x 50 μm.

Failure analysis of dynamic random access memory follows a three-step process consisting of electrical test and diagnosis, localization, and physical defect analysis. The electrical test delivers pass-fail results that are graphically displayed in bitmaps, which are then used to localize defects based on layout data. This article describes each step of the process and compares and contrasts laser scanning techniques.

This paper describes a methodology for preparing contoured devices by using a milling machine in conjunction with a spectral reflectance measurement system for meeting ±5 μm remaining silicon thickness (RST) tolerances.

Three case studies involving 14 nm SRAM technology show how progressive FIB cross-sectioning and top-down analysis can be supplemented with nanoprobing and TEM tomography to determine the root cause of failure. In the first case, the memory failure is traced to an abnormal gate profile. In the second case, the failure is attributed to a metal line short, and in the third case, a gate defect.

This article explains how hardware and software enhancements bring new capabilities to one of the most widely used soft-defect localization techniques. It discusses the basic concept of electrically enhanced laser-assisted device alteration (EeLADA) and demonstrates its use on different types of soft and hard defects. It also discusses the relative advantages of hardware and software implementations.

Wafer-level failure analysis plays an important role in IC fabrication, both in process development and yield enhancement. This article outlines the general flow for wafer-level FA and explains how it differs for memory and logic products. It describes the tools and procedures used for failure mode verification, electrical analysis, fault localization, sample preparation, chemical analysis, and physical failure analysis. It also discusses the importance of implementing corrective actions and tracking the results.

This article assesses the capabilities of failure analysis techniques in the context of 65 nm CMOS ICs. It demonstrates the use of OBIRCH, voltage contrast, Seebeck effect imaging, SEM and TEM techniques, and FIB cross-sectioning on failures such as dielectric breakdown, open and resistive vias, voids, shorts, delaminations, and gate oxide defects.

This article demonstrates the value of atomic force microscopes, particularly the different electrical modes, for characterizing complex microelectronic structures. It presents experimental results obtained from deep trench isolation (DTI) structures using SCM and SSRM analysis with emphasis on the voltage applied by the AFM. From these measurements, a failure analysis workflow is proposed that facilitates AFM voltage optimization to reveal the structure of cross-sectioned samples, make comparisons, and determine the underlying cause of failures.

With the growing complexity of new processes and the introduction of new materials, the need for product yield management and process control is placing unprecedented demands on failure analysis laboratories in the semiconductor industry. These demands are calling for faster and superior analytical capabilities to determine root-cause failure mechanisms in semiconductor devices fabricated using deep submicron processes. This article presents a new automated sample preparation technique that facilitates direct electrical contact to the area of interest, with a surface quality sufficient for scanning probe microscope analysis.

Coil failures can often be traced to an electrically open wire. In practice, coil wire breaks are the result of two or more failure mechanism acting together or in sequence. This article discusses the characteristics of different failure mechanisms and explains how to recognize them during analysis. Scanning electron micrographs of failed copper-wire ends presented in this article may be used as a guide in pinning down the cause of open-wire coil failures.

This article presents three failure analysis case histories involving the use of silver in electrical applications. The first two failures, that of a relay and a trimming potentiometer, highlight the incompatibilities of silver and sulfur. The third failure, in which several surface-mount resistors had shorted, is attributed to silver’s susceptibility to electrolytic migration.

This article presents a case study involving flash memory bit failures characterized by threshold voltage changes due to positive gate disturb stress. An inconsistency in failing bit behavior, which was found to be dependent on the test mode, was explored to provide an electrical explanation for the failure. The underlying defect was isolated and subsequently identified by physical analysis.

Scanning electron microscopes can be used to analyze almost anything that conducts electricity and is prone to failure, including relays, coils, inductors, capacitors, resistors, transistors, diodes, IGBTS, MOSFETS, and hybrid circuits. As the author of the article explains, SEMs are one of the most versatile tools for failure analysis if used to the full extent of their capabilities. Their operating modes include emissive imaging, backscattering, voltage contrast, EBIC or specimen current, and conductivity resistive mapping. The author describes each operating mode and presents examples of the various ways they can be used.

Many standard physical failure site isolation techniques require an electrical stimulus to drive test devices into a failing condition. This function has been provided by bench test electronics for some time, but increasing device complexity is causing a migration to more sophisticated equipment such as pattern generators and logic analyzers. In anticipation of further increases in pin count and density, a new class of small footprint testers is emerging. These portable systems, called ASIC verification testers, facilitate the transfer of ATE test programs to failure analysis laboratories at relatively low cost.

Electronic device failure analysis usually starts with electrical testing, followed by visual inspection via optical microscopy, then examination in a scanning electron microscope. When imaging reveals the need to determine the composition of materials, defects, and suspected contaminants, the electron beam produced by the SEM can be used to obtain the necessary information. As the article explains, this is the basic concept behind the method known as energy dispersive X-ray spectroscopy (EDS or EDX) and the key to its widespread use. In addition, the article presents three examples showing how SEM/EDS measurements helped failure analysts identify human contaminants on a die sample, determine the source of a particle embedded in the film stack on a wafer, and conclude that lead spatter from a solder die-attach preform caused wire bond lift.

Laser voltage imaging (LVI) enables the global visualization of on-chip circuit activity for the purpose of localizing defects. In a manner reminiscent of e-beam voltage contrast, it allows analysts to visually trace signals through circuit logic in order to see where faults occur. This article explains how laser voltage imaging works and how it is being used in semiconductor failure analysis. It also describes the types of applications for which LVI is not well suited.

Scanning capacitance microscopy (SCM) and nanoprobing are key tools for isolating and understanding transistor level fails. In this case study, SCM and nanoprobing are used to determine the electrical characteristics of cluster-type failures in 14 nm SOI FinFET SRAM after standard FIB cross-section imaging failed to reveal any visible defects.

Plasma focused ion beam (PFIB) systems can generate ion beams with much higher current and are therefore able to remove larger volumes of material at much faster rates while still maintaining precise control of the beam and its milling action. This article explains how the improved performance of PFIB is leading to new applications in delayering, deprocessing, and site-specific failure analysis.