Search Results for dynamic laser stimulation

Dynamic laser stimulation is widely used in the PASS/FAIL mapping mode for soft defect localization. Recent improvements, including parametric mapping and multiple-parameter acquisition, significantly increase the amount of information that can be extracted from DLS measurements. This article explains where and how these new techniques are used and how they may be even further improved.

A wide range of electrical faults are revealed through thermal laser stimulation (TLS). In principle, an electrical parameter, typically current or voltage, is monitored for changes caused by the heating effects of the laser. Most test setups are designed to limit the activity of the device in order to minimize the signal-to-noise ratio, but in some cases, the fault’s electrical footprint can only be detected when the device is stimulated in a dynamic way. This article describes the setup and implementation of various dynamic TLS methods and presents example applications demonstrating the advantages and limitations of each approach.

This column reviews a survey of the top ISTFA contributors from 1999 to 2008 and the topics addressed in their papers.

This article explains how hardware and software enhancements bring new capabilities to one of the most widely used soft-defect localization techniques. It discusses the basic concept of electrically enhanced laser-assisted device alteration (EeLADA) and demonstrates its use on different types of soft and hard defects. It also discusses the relative advantages of hardware and software implementations.

The power of scanning optical microscopes (SOMs) lies in their ability to direct a small spot of light into an IC, producing photocarriers and heat in a localized area of the circuit. Photonic and thermal energy affect the I-V characteristics of the circuit in different ways, depending on the presence of defects and local material properties. This article explains how light beams interact with semiconductors and metals and how they influence the I-V characteristic of circuits and devices. It describes the basic physics of SOM measurements, provides examples of static and dynamic SOM techniques, and discusses emerging applications.

This article describes a yield-driven approach for characterizing IC logic failures at the wafer level and presents several case studies to demonstrate its versatility and assess its value.

Selecting a fault isolation technique for a particular type of SRAM logic failure requires an understanding of available methods. In this article, the authors review common fault isolation techniques and present several case studies, explaining how they determined which technique to use.

This article provides a recap and summaries of the EDFAS Virtual User Group Workshop held in January 2021. The summaries cover key participants, presentation topics, and discussion highlights from the Focused Ion Beam, Sample Preparation, Contactless Probing and Nanoprobing, and System on Package virtual group meetings.

The 22nd European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF 2011) was held October 3 to 7, 2011, in Bordeaux, France. The conference concentrated on two main areas in electronics that concern designers, manufacturers, and users: (1) strategy for quality and reliability assessment of electronic circuits and systems, and (2) advanced analysis techniques for technology and product evaluation. This article reports on highlights of the technical program.

This column provides a ten-year retrospective on laser-based fault isolation techniques and the important role of laser signal injection microscopes.

Soft electrical failures caused by monograin defects can have a significant impact on yield in technology nodes below 40 nm. Moreover, the failures are hard to identify and the defects give very few signatures during localization testing. In this article, the authors explain how they used nanobeam diffraction with automated crystal orientation and phase mapping to pinpoint a single grain orientation causing the problem and, as a result, are now able to recognize the symptoms of this type of failure, observe the defect, and limit the impact on electrical timing margins through both design and process corrections.

Backside optical analysis is often aided by solid immersion lenses (SILs), but as the authors of this article explain, SILs improve the resolution of front side thermography as well. The authors describe the physics behind solid immersion lenses and provide examples that demonstrate the advantages and limitations of their use from the font side.

Failure analysis is becoming increasingly difficult with the emergence of 3D integrated packages due to their complex layouts, diverse materials, shrinking dimensions, and tight fits. This article demonstrates several FA techniques, including high-frequency scanning acoustic microscopy, lock-in thermography, and FIB cross-sectioning in combination with plasma ion etching or laser ablation. Detailed case studies show how the various methods can be used to analyze bonding integrity between different materials, chip-to-chip interface structures, buried interconnect defects, and through-silicon vias at either the device or package level.

Failure analysis of dynamic random access memory follows a three-step process consisting of electrical test and diagnosis, localization, and physical defect analysis. The electrical test delivers pass-fail results that are graphically displayed in bitmaps, which are then used to localize defects based on layout data. This article describes each step of the process and compares and contrasts laser scanning techniques.

This article explains how laser voltage probing (LVP) can be used to analyze combinational logic circuits. The authors describe how the technique is aided by the development and use of a waveform library and a corresponding truth table. They also present a case study in which the new technique is used to isolate faults in a combinational logic circuit consisting of multiple gates.

Metrology targets are an essential tool for evaluating the performance of imaging systems and maintaining their accuracy over time. Ideally, the pattern on the target is simple enough that the expected image is intuitive or, at least, easily simulated. Although many such targets exist for frontside imaging, until recently, few if any could be found for backside applications. In this article, the first of a two-part series, the authors explain how they addressed this gap by converting a readily available frontside target for backside use. The conversion process is described step by step in enough detail that it can be replicated in order to convert other frontside targets. Due to the success of the converted target, an unmounted, backside-specific version has subsequently been developed, the availability of which not only eliminates one of the more difficult steps in the original conversion process, but also provides additional benefits. Using one of these newer targets, the authors evaluated a backside imaging system consisting of a laser scanning microscope (LSM) and a solid immersion lens (SIL). The results are presented here along with the criteria used for the evaluation. Other applications of the new metrology target as well as its limitations are discussed in the May 2015 issue of EDFA .

This article explains how the success rate of in-line scan chain logic macros can be nearly doubled for certain types of failures with the help of laser voltage imaging and laser voltage probing. The authors provide background information on LVI, LVP, and scan chain logic macros and show how they are used to diagnose skip test, clock-type, and soft single-latch failures.

In many companies, failure analysis (FA) has evolved to mean much more than analyzing a part from yesteryear and filing a report simply to satisfy a requirement. Failure analysis engineers frequently interface with design, test, and product engineering and are an integral part of yield improvement. This article addresses several common misperceptions about the failure analysis process.

This article presents a recent breakthrough in the use of machine learning in semiconductor FA. For the first time, cell-internal defects in FinFETs have not only been detected and diagnosed, but also refined, clarified, and resolved using cell-aware diagnosis along with root cause deconvolution (RCD) techniques. The authors describe the development of the methodology and evaluate the incremental improvements made with each step.

Over the last few years, new challenges increased the pressure on packaging and assembly analytical resources. Reduced product development cycle time, increased market segmentation, new package and die level materials, ever shrinking device geometries, and fully enabled technologies (i.e. with thermal, retention, and EMI solutions) created these new pressures on fault isolation/failure analysis efforts and package development.