Failures of interest in this article usually occur on single-sided, non-plated-through-hole circuit boards. Evidence of failure may be as subtle as crazing (a pattern of small surface cracks) of solder-joint surfaces or as catastrophic as burning of the circuit board. Over time, crazing coalesces into circumferential cracks in the solder joint, and these cracks deepen until catastrophic failure occurs.

This article discusses the challenges involved in testing analog and mixed-signal ICs and provides practical guidance and insights on how to deal with them.

Semiconductor trends, as embodied in the International Technology Roadmap for Semiconductors (ITRS), provide a guide for the challenges facing the failure analysis community. This process is a risk assessment of key features forecast for the impact of future technologies on failure analysis. The technical challenges fall primarily into two categories: failure site isolation and physical analysis. The failure site isolation challenges are largely driven by the device complexity and reduced accessibility of circuit nets. Additional challenges arise due to the increase in device operating speed and pin count. The challenges in physical analysis are driven primarily by smaller device feature sizes and by the host of new materials being introduced. In addition to the technical challenges, infrastructure changes are also likely to occur. The industry paths for addressing these challenges are discussed.

Many standard physical failure site isolation techniques require an electrical stimulus to drive test devices into a failing condition. This function has been provided by bench test electronics for some time, but increasing device complexity is causing a migration to more sophisticated equipment such as pattern generators and logic analyzers. In anticipation of further increases in pin count and density, a new class of small footprint testers is emerging. These portable systems, called ASIC verification testers, facilitate the transfer of ATE test programs to failure analysis laboratories at relatively low cost.

Thin film anomalies cause many device failures but they are often difficult to see. In this article, the authors explain how they found and identified an 8 to 10 nm film of tantalum causing pin shorts in a majority of ASIC modules from a particular lot. Initial attempts to delayer some of the failed modules resulted in the loss of the failure signal. It was then decided to use a focused ion beam to selectively mill through the interlayer dielectric. During milling, a secondary electron image revealed anomalous material between the fingers of a power transistor, which was subsequently identified as tantalum. Such defects, as the authors explain, are common in damascene processes when materials are not properly removed during etching.

A string of failures discovered during final testing after assembly led analysts on a long search for the cause, which turned out to be an unusual form of electrostatic discharge (ESD). Most ESD impacts on ICs occur by way of the pins. Nearly all ESD models, including the widely used human body model, charged-device model, and machine model, are based on this assumption. However, as this case study proves, passivated wafers and unpackaged dies are also susceptible to ESD damage. The authors explain that although this type of failure is difficult to diagnose, they were able to pinpoint the cause using lock-in microthermography and rule out mechanical-, FIB-, and laser-induced failures, which are similar in appearance.

In this case study, the author describes the investigation of a defective DC-DC converter retrieved from an aircraft following the report of abnormal system behavior. Electrical testing, local probing, X-ray imaging, and cross-sectional analysis led to the discovery of cracks on several pins and in some of the solder material. The cracks were caused by different rates of thermal expansion and were remedied with the help of thermomechanical analysis, EBSD imaging, and phase map comparisons for thick and thin solder joints.

This article describes how focused ion beam (FIB) technology is being used in combination with various other analytical tools for failure and yield analysis of MEMS devices. It provides examples showing how FIB is used with TEM analysis, AFM analysis, scanning acoustic microscopy, and scanning laser microscopy.

Techniques used by failure analysts to provide proper stimuli to diagnose failures in mixed-signal ICs differ from routine digital IC tester stimuli. Mixed-signal parts not only require vector stimulus (i.e., set timing and frequency base), but also analog output sense signals, which are classified by differences in magnitude, frequency, and current. This article explains how a mixed-signal ASIC was analyzed using various signal stimuli.

Time domain reflectometry (TDR) is widely used to measure the electrical length of conductors. It has also proven useful for isolating failures in ICs. This article describes a variation of the method, called comparative TDR, that overcomes inherent timing limitations and simplifies use. It discusses the basic hardware requirements of the new technique and presents examples demonstrating its use on opens and shorts in ceramic flip-chip packages.

Latchup has long been a concern for CMOS technologies and is becoming more of an issue with the reduction of transistor dimensions and spacing. Although many techniques for avoiding the risk of latchup have been developed, they generally apply to specific technologies and are not portable to others. In light of the problem, IBM engineers conducted an in-depth evaluation of the structures most sensitive to latchup ignition and the many possible triggering mechanisms. In this article, they describe the work they performed along with the findings and provide practical guidelines on how to minimize latchup regardless of the IC technology involved.

This article explains how hardware and software enhancements bring new capabilities to one of the most widely used soft-defect localization techniques. It discusses the basic concept of electrically enhanced laser-assisted device alteration (EeLADA) and demonstrates its use on different types of soft and hard defects. It also discusses the relative advantages of hardware and software implementations.

This article provides a detailed overview of silicon characterization and debug process, describing the intent of each step, the challenges involved, and the FA tools and techniques used. It also discusses the difference between electrical and functional failures, the implementation and use of on-chip debugging resources, the important role of schmoo plots.

Single contact optical beam induced currents (SCOBIC) is a variation on the OBIC failure analysis technique that requires only one point of contact with the junction being examined. This article discusses the basic principles of this new method and how it compares with OBIC in terms of measurement performance. It also presents examples showing how SCOBIC can be used to analyze CMOS devices from the front and back side without need for complex FIB and microprobing procedures.

Scanning laser-SQUID microscopy is a new electrical inspection and failure analysis technique that can detect open, high-resistance, and shorted interconnects without electrical contact in areas ranging in size from a few square microns to an entire die. This article describes the setup of a prototype laser-SQUID system, explaining how it works and how it compares to other nondestructive defect localization techniques. It presents application examples in which laser-SQUID microscopy is used to locate gate oxide shorts to within 1.3 μm and detect IC defects prior to bond-pad pattering and after bonding and packaging. It also includes a series of images acquired from a board-mounted chip with fields of view ranging from 5 x 5 mm down to 50 x 50 μm.

Chip-scale packages (CSPs) make efficient use of space on PCBs, but their small size, multilevel stacking arrangements, and complex interconnects present serious challenges when it comes to testing and failure analysis. This article describes some of the problems encountered when dealing with various types of CSPs and provides practical solutions based on the tools and techniques available in most FA labs. It discusses the causes and effects of package and die related failures and walks readers through the steps involved in decapsulating plastic FBGA packages using conventional etching, polishing, and milling techniques.

Automotive electronics are exposed to mechanical shock and vibration, thermal cycling, chemical attack, current and voltage spikes, electromagnetic interference, and other hazards. Early life failures, which are not uncommon, can be difficult to diagnose due to the many contributing factors. This article provides an overview of automotive electronic failures and presents guidelines for determining the root cause.

This column addresses the different perspectives of providers and customers of semiconductor failure analysis laboratories. The columnist, after having seen both sides of the electronics industry, as a supplier and customer, sheds light on how the two sides interact when entangled with reliability issues and failures.

Circuit boards are vulnerable to a wide range of ill-intentioned modifications done to gain access to information or malevolently influence control. This article describes the various ways attacks on circuit board can occur and presents examples showing how such attacks might look. It also provides general guidelines for protecting circuit-board design integrity.

The reliability of a component is the probability that it will perform its function under specified conditions for a specified length of time. Key considerations in defining and designing reliability tests are reviewed in this article, which also discusses the interpretation of test results.