This article explains how the addition of FIB tunable circuits in critical paths on ICs can alleviate some of the challenges encountered during the implementation of mixed-signal ASICs. It walks readers through the implementation of a particular digital ASIC, explaining where and how FIB tunable circuits were used to overcome difficulties, resolve problems, and realize a fully functional chip that met all system specifications on the first pass of the design.

Soft electrical failures caused by monograin defects can have a significant impact on yield in technology nodes below 40 nm. Moreover, the failures are hard to identify and the defects give very few signatures during localization testing. In this article, the authors explain how they used nanobeam diffraction with automated crystal orientation and phase mapping to pinpoint a single grain orientation causing the problem and, as a result, are now able to recognize the symptoms of this type of failure, observe the defect, and limit the impact on electrical timing margins through both design and process corrections.

Faster time-to-production of a new product is the common goal of design houses and foundries. This article demonstrates how foundries can contribute through post silicon validation, which allows design houses to focus on more complicated issues.

This article explains how hardware and software enhancements bring new capabilities to one of the most widely used soft-defect localization techniques. It discusses the basic concept of electrically enhanced laser-assisted device alteration (EeLADA) and demonstrates its use on different types of soft and hard defects. It also discusses the relative advantages of hardware and software implementations.

In most cases, microelectronic failure analysis is rooted in the observation of voltage, either as logic levels or as time-based waveforms. This is due largely to the ease of making such measurements. As a result, current measurement is often overlooked. This article discusses aspects of current measurement that can be used during fault localization, often providing information that cannot be obtained by other means.

ICs designed for portable devices often make use of reverse-body bias (RBB) modes to limit leakage currents. The added complexity of RBB support circuitry presents a challenge during IC characterization and debug. This article discusses the nature of the problem and explains how to identify irregularities in circuits operating in the body-biased condition using standard debug tools with simple modifications. It describes some of the bugs discovered in an actual examination and explains how they were diagnosed by analyzing I-V curve traces and infrared emission microscopy (IREM) images.

The reliability of a component is the probability that it will perform its function under specified conditions for a specified length of time. Key considerations in defining and designing reliability tests are reviewed in this article, which also discusses the interpretation of test results.

This article provides a detailed overview of silicon characterization and debug process, describing the intent of each step, the challenges involved, and the FA tools and techniques used. It also discusses the difference between electrical and functional failures, the implementation and use of on-chip debugging resources, the important role of schmoo plots.

This article examines some of the major forces reshaping the microelectronics industry. It begins with a summary of how the industry has worked up to now. It then describes the economic, processing, and device physics challenges looming on the horizon and explains how the industry is gearing up to meet them. It also discusses the implications of these changes on failure analysis.

This article provides a summary of each of the four User’s Group meetings that took place at ISTFA 2011. The summaries cover key participants, presentation topics, and discussion highlights from each of the following groups: Group 1, Focused Ion Beam; Group 2, 3D Packaging and Failure Analysis; Group 3, Finding the Invisible Defect; and Group 4, Nanoprobing and Electrical Characterization.

Fluid-filled metallized-polymer-film capacitors have unique failure mechanisms, many of which are related to insufficient fluid level, improper installation geometry, or both. Although such failures can be analyzed using X-ray testing equipment, it is often impractical or cost-prohibitive. This article describes some of the failure modes observed in fluid-filled capacitors and explains how to analyze them easily and inexpensively.

A review of the 2001 edition of the International Technology Roadmap for Semiconductors indicates major obstacles ahead. Of the three basic failure analysis steps—inspection, deprocessing, and fault isolation—the latter is the most at risk, especially physical fault isolation.

Four panel members participated in the ISTFA 2014 Panel Discussion on the importance of correctly determining the cause of failure in electronic devices and systems designated for use in space, downhole drilling, and other such applications. Reliability of these components is critical because they cannot be easily replaced and malfunctions can be catastrophic. The panelists presented several methods for analyzing failures in integrated electrical systems and identifying the root cause.

This column explains what it takes to set up and run a successful foundry-based failure analysis laboratory.

The EDFAS Board of Directors (BOD) has undertaken an initiative to help drive the development of failure analysis methods as leading-edge semiconductor technology approaches the sub-20 nm regime. To streamline efforts and leverage existing work, the BOD recently surveyed its constituency to gauge their opinions on the capability gaps identified by the Sematech councils. This article briefly discusses the methodology of the survey and provides a summary of the responses along with key findings.

Unit level traceability (ULT) is a powerful tool that allows complete die histories to be accessed in the course of testing and analysis. It is especially useful for identifying the likely causes of microprocessor failures and in cases where failure analysis resources are limited. In the article, the author explains how he used ULT in the investigation of a 0.25-µm CMOS processor. Using the ULT of the die, he discovered a failure signature based on die location on the wafer. One root cause of failure was traced to cross-field variation in the lithography process due to marginal focus control. Another failure, observed after burn-in, was traced to the presence of residual titanium left after metal etch.

The susceptibility of ICs to electromagnetic interference is a growing concern for both designers and failure analysts. This article discusses the causes and effects of transient electromagnetic interference and the factors that influence electromagnetic susceptibility. It explains how to determine susceptibility based on transient pulse testing and presents and interprets the test results of three automotive ICs.

Shmoo plotting began in the early 1970s and still has wide use in characterizing device performance against various parameters. Typically, Shmoo plots measure device frequency or cycle time versus voltage. The debug described in this article focused on problems (holes) in Shmoo plots discovered while designing a 637-MHz microprocessor. This problem had two distinct phases as the microprocessor design migrated from an older CMOS process technology into a newer, faster one. Resolution of the problem, as the article explains, required advanced DFD/DFT (design for debug/design for test) techniques and FIB circuit edit to resolve.

This column explains that, contrary to rumors, photon emission is alive and well and about to enrich FA even further if a few new approaches pan out.

Voltage contrast, a phenomenon that occurs in scanning electron microscopes, produces brightness variations in SEM images that correspond to potential variations on the test sample. Through appropriate processing, voltage contrast signals can reveal an extensive amount of information about the functionality of ICs. Voltage contrast can be used, for example, to map electrical logic levels and timing waveforms from internal nodes of the chip as it operates inside the SEM chamber. This article describes the fundamentals of voltage contrast and its applications in IC failure analysis.