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design margins

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Journal Articles
EDFA Technical Articles (2004) 6 (2): 6–11.
Published: 01 May 2004
... and how FIB tunable circuits were used to overcome difficulties, resolve problems, and realize a fully functional chip that met all system specifications on the first pass of the design. Copyright © ASM International® 2004 2004 ASM International critical timing paths design margins FIB tunable...
Journal Articles
EDFA Technical Articles (2018) 20 (1): 10–18.
Published: 01 February 2018
... margins through both design and process corrections. Soft electrical failures caused by monograin defects can have a significant impact on yield in technology nodes below 40 nm. Moreover, the failures are hard to identify and the defects give very few signatures during localization testing...
Journal Articles
EDFA Technical Articles (2017) 19 (4): 22–34.
Published: 01 November 2017
... types of design bugs. Logic or functional bugs are caused by design errors or insufficient validation coverage. Electrical or circuit bugs that manifest under certain operating conditions can be caused by design marginalities and process variations. As a statistical reference, it was reported...
Journal Articles
EDFA Technical Articles (2016) 18 (3): 10–16.
Published: 01 August 2016
... INTRODUCTION On sub-28 nm process technology, silicon patterning conformance to design, especially front-end-of-line, has run up against the limits of physics, bringing about a paradigm shift from defect-limited hard failures to increasing occurrences of design-margin soft failures as a result of the shrinking...
Journal Articles
EDFA Technical Articles (2007) 9 (3): 18–20.
Published: 01 August 2007
... biasing within a circuit block. Since any circuit design relies on proper biasing to operate as intended, marginalities in the references established within a circuit can cause failures that are maddeningly difficult to pinpoint. As an example, consider a basic oscillator circuit. Such a circuit typically...
Journal Articles
EDFA Technical Articles (2004) 6 (1): 13–21.
Published: 01 February 2004
... margin. Test and Design Issues Fig. 4 (a) Measured state loss voltage versus regulator voltage and (b) with margin current sourced nominally doubling the standby current. The figure clearly shows that added current can be used to introduce a testing guardband. Depending on the design, some circuit blocks...
Journal Articles
EDFA Technical Articles (2008) 10 (1): 18–22.
Published: 01 February 2008
... the onset of wearout should be beyond the useful life of the product, it is not necessarily so. Safety margins have decreased through design rule changes to minimize size. The need for narrow metal lines pushes limits for maximum current density. Bond wire diameter must be maintained for low resistance...
Journal Articles
EDFA Technical Articles (2003) 5 (3): 5–11.
Published: 01 August 2003
... but not others. Electrical characterization is focused on guaranteeing the robustness of the device across voltage, frequency, temperature, and silicon processing variations. It is useful to vary all of these parameters during characterization to expose electrical design marginalities. Volume 5, No. 3 Electronic...
Journal Articles
EDFA Technical Articles (1999) 1 (4): 6–25.
Published: 01 November 1999
... FAILURE ANALYSIS NEWS acinurrenter/ "killer applications" (e.g., voice recognition) that will provide new markets for high profit margin devices. Processing Challenges There are nwnerous processing challenges including affordable post-optical lithography, processing with reduced thermal budgets...
Journal Articles
EDFA Technical Articles (2012) 14 (1): 27–31.
Published: 01 February 2012
... on a hemispherical design and a gridded Fresnel-type lens. Both lenses improved the image, but both also suffered from interference fringes. More work will be done on refining this application. Valery Ray presented novel chemistry and patterning techniques to optimize large copper line removal for deprocessing ICs...
Journal Articles
EDFA Technical Articles (2007) 9 (2): 6–12.
Published: 01 May 2007
... a small part of the housing wall and because the new containment surface (i.e., the tape) is flush with the outside of the housing, the measured fluid level will be slightly lower than the level in the undisturbed housing. Of course, if the fluid level is marginal (e.g., Fig. 13), then the top...
Journal Articles
EDFA Technical Articles (2002) 4 (4): 5–9.
Published: 01 November 2002
...-fail maps and logic diagnostics are available with proper design-for-test (DFT) strategies. But physical fault isolation methods like photon emission, OBIRCH, LIVA, etc., are unique to IC failure analysis. If we don t drive development, chances are no one else will. The Roadmap The Roadmap forecasts...
Journal Articles
EDFA Technical Articles (2015) 17 (1): 32–33.
Published: 01 February 2015
...Felix Beaudoin; David Grosjean Four panel members participated in the ISTFA 2014 Panel Discussion on the importance of correctly determining the cause of failure in electronic devices and systems designated for use in space, downhole drilling, and other such applications. Reliability...
Journal Articles
EDFA Technical Articles (2011) 13 (4): 50–51.
Published: 01 November 2011
... diagnosis data. A foundry FA lab can possibly handle dynamic fault isolation tasks by software, hardware, and the analyzed diagnosis data supported by customer engineering resources under a design-for-manufacturing concept. Layout navigation and net-list tracking are essential capabilities empowering...
Journal Articles
EDFA Technical Articles (2010) 12 (2): 29–32.
Published: 01 May 2010
... margins, and higher power are pushing many instruments to the limits of their capability, while others have already started to fall behind. While marginal progress has been made in some areas, development and commercialization of new solutions for the toughest analytical problems does not appear imminent...
Journal Articles
EDFA Technical Articles (2000) 2 (3): 1–10.
Published: 01 August 2000
.... In the article, the author explains how he used ULT in the investigation of a 0.25-µm CMOS processor. Using the ULT of the die, he discovered a failure signature based on die location on the wafer. One root cause of failure was traced to cross-field variation in the lithography process due to marginal focus...
Journal Articles
EDFA Technical Articles (2006) 8 (4): 16–24.
Published: 01 November 2006
... to a ±200 mV noise margin. The amount of noise required to cause a malfunction can vary widely from one IC design to another. toward possible points of entry of the IC: inputs, outputs, peripheral and core supplies, or via the common substrate. One reason for investigating susceptibility to impulse...
Journal Articles
EDFA Technical Articles (2000) 2 (4): 13–16.
Published: 01 November 2000
... Problem resided in this same mismatched WCONRS inverter delay chain. Since the older CMOS6X design problem was marginal, the subtle SRAM cell defects were required to bring the L1 Cache design to failure. The faster CMOS7S process had pushed the new design such that the slow inverter chain no longer...
Journal Articles
EDFA Technical Articles (2012) 14 (4): 46–47.
Published: 01 November 2012
..., the alarming message concerned its marginal evidence. In fact, the voltage-dependent photon emission intensities were studied on devices designed for exactly one supply voltage. When voltages smaller than nominal are applied, it may not be as significant as predicted for technologies designed for those smaller...
Journal Articles
EDFA Technical Articles (2001) 3 (3): 15–18.
Published: 01 August 2001
.... The measurement electronics have low bandwidth and can be designed for low noise. This approach has several drawbacks. First, the measurements require that the chip exercise a precise repeating test loop. A complex processor may need significant internal set-up before a failure is made visible, and this could...