Although much traditional FA depends on physical observation to localize failures, electrical techniques are also important, particularly with advances in design for testability (DFT) on modern ICs. DFT structures combined with automated test equipment and algorithmic fault diagnosis facilitate a test-based fault localization (TBFL) approach to identify defect locations on ICs based on scan test patterns. This article and a companion piece in the November 2001 issue of EDFA provide an overview these methods and show how they can reduce the number of potential defect sites on a chip and, in some cases, identify defects that would be missed by other techniques.

A new product-like test chip developed by engineers at Carnegie Mellon University overcomes the current limitations in conventional test chip design. This article discusses the advantages of the new chip, called the CM-LCV, and presents experimental results showing how it achieves fault coverages comparable to or better than benchmarking designs.

How does one decide the most significant work published in a conference after 35 years? What selection criteria should be used, and why go through the exercise in the first place? This article addresses the evaluation criteria and includes the list of forty selected significant ISTFA papers published between 1979 and 2002.

The EDFAS Die-Level Roadmap Committee was formed to identify forthcoming challenges related to electrical fault isolation within the next five years and collaborate with various stakeholders, including industry, academia, and tool vendors, to devise practical solutions. To that end, the team has pinpointed five critical areas of focus: (1) laser-based, photon emission, and thermal; (2) 2D/2.5D/3D packaging; (3) product yield, test, and diagnostics; (4) general (leading edge technologies); and (5) system level, analog/RF, and digital functional.

This article describes a yield-driven approach for characterizing IC logic failures at the wafer level and presents several case studies to demonstrate its versatility and assess its value.

This column commemorates the life and career of Jack Kilby, who passed away June 20, 2005. Kilby was the keynote speaker for the 25th anniversary of the ISTFA conference in 1999 and in 2000 was awarded the Nobel Prize in Physics for his part in the invention of the integrated circuit in 1958.

CMOS IC failure mechanisms are of three general types: bridge defects, open circuit defects, and parametric related failures. This article summarizes bridge and open-circuit defect properties and provides references for further self-study. Bridge defects are characterized based on location, their significance in terms of logic gates and transistors, and critical resistance for dc logic and timing failures. Open defects are more complex and diverse with six possible failure modes each of which are described in the article.

This is the second article in a two-part series on test-based failure analysis (TBFA). The first article, which appeared in the August 2001 issue of EDFA, discussed the need for automated diagnostics and the general concept of TBFA. This article discusses the steps involved in implementing a TBFA process and addresses the challenges that are likely to be encountered. It explains how to gather data required to link observed behavior to specific faults, how to set up and use fault dictionaries, and how to handle unmodeled as well as bridging faults. It also discusses the use of TBFA with conventional voltage and quiescent current (IDDQ) testing.

The organizer and moderator of the ISTFA 2007 panel discussion on failure analysis and testing of medical devices provide a summary of the discussion topics and areas of focus.

This article presents the results of a study conducted at Sandia National Labs to assess the effect of electrostatic discharge on surface micromachined MEMS devices. This failure mode has largely been overlooked because ESD failure mechanisms often mimic the effects of stiction-adhesion. To measure the susceptibility of MEMS devices to ESD, Sandia engineers built and tested a silicon microengine and a torsional ratcheting microactuator. Test results indicate that the effects of ESD are highly dependent on device design, component stiffness, and geometry and that slight modifications can bring improvements.

This article provides a detailed overview of silicon characterization and debug process, describing the intent of each step, the challenges involved, and the FA tools and techniques used. It also discusses the difference between electrical and functional failures, the implementation and use of on-chip debugging resources, the important role of schmoo plots.

Picosecond imaging circuit analysis (PICA) is an advanced diagnostic technique that measures device switching activity on CMOS ICs through the backside of the die. Due to its relatively large field of view, it can quickly locate defects among large numbers of candidates. In this case study, the authors explain how they used PICA to identify a particular I/O circuit defect on the IBM System/390 G5 microprocessor. They also explain how they verified the diagnostic result using circuit simulations.

Shmoo plotting began in the early 1970s and still has wide use in characterizing device performance against various parameters. Typically, Shmoo plots measure device frequency or cycle time versus voltage. The debug described in this article focused on problems (holes) in Shmoo plots discovered while designing a 637-MHz microprocessor. This problem had two distinct phases as the microprocessor design migrated from an older CMOS process technology into a newer, faster one. Resolution of the problem, as the article explains, required advanced DFD/DFT (design for debug/design for test) techniques and FIB circuit edit to resolve.

Government and military ICs, like their commercial counterparts, are subject to ever-tightening cost, performance, and time-to-market demands. They must also comply with strict lifetime, reliability, and radiation hardness standards. In dealing with these challenges for internal applications, engineers at Sandia National Laboratories developed a radiation-hardened structured ASIC platform. In this article, they describe the design and development of the platform and the associated challenges for FA and test.

This article explains how the addition of FIB tunable circuits in critical paths on ICs can alleviate some of the challenges encountered during the implementation of mixed-signal ASICs. It walks readers through the implementation of a particular digital ASIC, explaining where and how FIB tunable circuits were used to overcome difficulties, resolve problems, and realize a fully functional chip that met all system specifications on the first pass of the design.

Advancements in photodetector technology are revitalizing time-resolved emission (TRE) techniques in semiconductor failure analysis. In this article, the authors explain how superconducting single-photon detectors improve the capabilities of TRE measurements as demonstrated on 14 nm FinFET technology and an inverter chain with power supply voltages down to 0.4 V.

Parametric analysis of SRAM cells is widely used to locate faults and analyze device failures, but the pico-probing and bit-line multiplexing required for data acquisition is becoming increasingly difficult. This article explains how the addition of an on-die low-yield analysis circuit eliminates the problem. The simplicity of the measurement circuit and the potential to use a known library of curves, makes low-yield analysis one of the most versatile DFT techniques for cache fault isolation.

This article provides insights into the nature of IDDQ and timing defects and the challenges they present to failure analysts based on the findings of a Sematach study.

This article discusses the causes and effects of stuck-open faults (SOFs) in nanometer CMOS ICs. It addresses detection and localization challenges and explains how resistive contacts and vias and the use of damascene-copper processes contribute to the problem. It also discusses layout techniques that reduce the likelihood of SOF failures.

Faster time-to-production of a new product is the common goal of design houses and foundries. This article demonstrates how foundries can contribute through post silicon validation, which allows design houses to focus on more complicated issues.