Although much traditional FA depends on physical observation to localize failures, electrical techniques are also important, particularly with advances in design for testability (DFT) on modern ICs. DFT structures combined with automated test equipment and algorithmic fault diagnosis facilitate a test-based fault localization (TBFL) approach to identify defect locations on ICs based on scan test patterns. This article and a companion piece in the November 2001 issue of EDFA provide an overview these methods and show how they can reduce the number of potential defect sites on a chip and, in some cases, identify defects that would be missed by other techniques.

A new product-like test chip developed by engineers at Carnegie Mellon University overcomes the current limitations in conventional test chip design. This article discusses the advantages of the new chip, called the CM-LCV, and presents experimental results showing how it achieves fault coverages comparable to or better than benchmarking designs.

How does one decide the most significant work published in a conference after 35 years? What selection criteria should be used, and why go through the exercise in the first place? This article addresses the evaluation criteria and includes the list of forty selected significant ISTFA papers published between 1979 and 2002.

The organizer and moderator of the ISTFA 2007 panel discussion on failure analysis and testing of medical devices provide a summary of the discussion topics and areas of focus.

Picosecond imaging circuit analysis (PICA) is an advanced diagnostic technique that measures device switching activity on CMOS ICs through the backside of the die. Due to its relatively large field of view, it can quickly locate defects among large numbers of candidates. In this case study, the authors explain how they used PICA to identify a particular I/O circuit defect on the IBM System/390 G5 microprocessor. They also explain how they verified the diagnostic result using circuit simulations.

This is the second article in a two-part series on test-based failure analysis (TBFA). The first article, which appeared in the August 2001 issue of EDFA, discussed the need for automated diagnostics and the general concept of TBFA. This article discusses the steps involved in implementing a TBFA process and addresses the challenges that are likely to be encountered. It explains how to gather data required to link observed behavior to specific faults, how to set up and use fault dictionaries, and how to handle unmodeled as well as bridging faults. It also discusses the use of TBFA with conventional voltage and quiescent current (IDDQ) testing.

Advancements in photodetector technology are revitalizing time-resolved emission (TRE) techniques in semiconductor failure analysis. In this article, the authors explain how superconducting single-photon detectors improve the capabilities of TRE measurements as demonstrated on 14 nm FinFET technology and an inverter chain with power supply voltages down to 0.4 V.

This article explains how the addition of FIB tunable circuits in critical paths on ICs can alleviate some of the challenges encountered during the implementation of mixed-signal ASICs. It walks readers through the implementation of a particular digital ASIC, explaining where and how FIB tunable circuits were used to overcome difficulties, resolve problems, and realize a fully functional chip that met all system specifications on the first pass of the design.

Parametric analysis of SRAM cells is widely used to locate faults and analyze device failures, but the pico-probing and bit-line multiplexing required for data acquisition is becoming increasingly difficult. This article explains how the addition of an on-die low-yield analysis circuit eliminates the problem. The simplicity of the measurement circuit and the potential to use a known library of curves, makes low-yield analysis one of the most versatile DFT techniques for cache fault isolation.

This article describes a yield-driven approach for characterizing IC logic failures at the wafer level and presents several case studies to demonstrate its versatility and assess its value.

This column commemorates the life and career of Jack Kilby, who passed away June 20, 2005. Kilby was the keynote speaker for the 25th anniversary of the ISTFA conference in 1999 and in 2000 was awarded the Nobel Prize in Physics for his part in the invention of the integrated circuit in 1958.

Off-state leakage currents account for roughly half of the total current is today’s ICs, and with each new generation of technology, the problem is getting worse. Failure analysts, however, see things differently. Light emission associated with leakage current is a rich source of information about the operation of ICs. In this article, the authors explain how they use this light to monitor logic states, measure temperatures, analyze cross-talk and power distribution noise, and diagnose broken scan chains. Light emission from off-state leakage current (LEOSLC) is shown to be especially useful for diagnosing faults that reside in scan clock trees, which are otherwise very difficult to detect.

CMOS IC failure mechanisms are of three general types: bridge defects, open circuit defects, and parametric related failures. This article summarizes bridge and open-circuit defect properties and provides references for further self-study. Bridge defects are characterized based on location, their significance in terms of logic gates and transistors, and critical resistance for dc logic and timing failures. Open defects are more complex and diverse with six possible failure modes each of which are described in the article.

Faster time-to-production of a new product is the common goal of design houses and foundries. This article demonstrates how foundries can contribute through post silicon validation, which allows design houses to focus on more complicated issues.

Engineers at IBM’s Watson Research Center are contending with one of the most fundamental limitations of imaging technology: the tradeoff between spatial resolution and field of view. In this article, they explain how they created tool interfaces, control and automation software, and image analysis and stitching algorithms, enabling photon emission and laser scanning microscopes to produce high-resolution mosaic images of advanced processor cores and other large-area ICs. They describe some of the challenges they faced and explain how their technology can be used to create images based on reflected light, induced voltage, photon emission, and laser stimulation signatures. In one of the latest demonstrations, the technology was used to land and focus a SIL more than 4000 times, acquiring some 16,000 images that were composed into stitched mosaics of several hundred images each.

This article assesses the capabilities of failure analysis techniques in the context of 65 nm CMOS ICs. It demonstrates the use of OBIRCH, voltage contrast, Seebeck effect imaging, SEM and TEM techniques, and FIB cross-sectioning on failures such as dielectric breakdown, open and resistive vias, voids, shorts, delaminations, and gate oxide defects.

This article provides a detailed overview of silicon characterization and debug process, describing the intent of each step, the challenges involved, and the FA tools and techniques used. It also discusses the difference between electrical and functional failures, the implementation and use of on-chip debugging resources, the important role of schmoo plots.

This article presents the results of a study conducted at Sandia National Labs to assess the effect of electrostatic discharge on surface micromachined MEMS devices. This failure mode has largely been overlooked because ESD failure mechanisms often mimic the effects of stiction-adhesion. To measure the susceptibility of MEMS devices to ESD, Sandia engineers built and tested a silicon microengine and a torsional ratcheting microactuator. Test results indicate that the effects of ESD are highly dependent on device design, component stiffness, and geometry and that slight modifications can bring improvements.

Scan-logic diagnosis is used in industry for three main purposes: root-cause analysis, improving manufacturing processes, and improving designs. This article reviews the principles of scan-logic diagnosis and its applications in each of the three areas. It also discusses ongoing challenges and emerging approaches.

Latchup has long been a concern for CMOS technologies and is becoming more of an issue with the reduction of transistor dimensions and spacing. Although many techniques for avoiding the risk of latchup have been developed, they generally apply to specific technologies and are not portable to others. In light of the problem, IBM engineers conducted an in-depth evaluation of the structures most sensitive to latchup ignition and the many possible triggering mechanisms. In this article, they describe the work they performed along with the findings and provide practical guidelines on how to minimize latchup regardless of the IC technology involved.