Traditional post-fabrication testing can reliably verify whether or not an IC is working correctly, but it cannot tell the difference between an authentic and counterfeit chip or recognize design changes made with malicious intent. This article presents an IC decomposition workflow, based on FA tools and techniques, that provides a quantifiable level of assurance for components in a zero trust environment.

Further development of SEM-based feature extraction tools for design validation and failure analysis is contingent on reliable sample preparation methods. This article describes how a delayering framework for 130 nm technology was adapted and used on a 45 nm SPI module consisting of 11 metal layers, 10 via layers, two layers of polysilicon, and an active silicon layer. It explains how different polishing and etching methods are used to expose each layer with sufficient contrast for SEM imaging and subsequent feature extraction. By combining polygon sets representing each layer, the full design of the device was reconstructed as shown in one of the images.

Counterfeit electronic parts have become a significant cause of concern in the electronics part supply chain. Several factors that contribute to the targeting of the electrical, electronic, and electromechanical (EEE) parts market by counterfeiters include parts obsolescence, extended lead times, the absence of verification tools, the availability of scrapped or salvaged parts, and the high costs associated with inspection/testing procedures. This article reports on the status of efforts by the G-19 Committee of SAE International to develop standards in response to increasing numbers of counterfeit parts in the supply chain.

ICs designed for portable devices often make use of reverse-body bias (RBB) modes to limit leakage currents. The added complexity of RBB support circuitry presents a challenge during IC characterization and debug. This article discusses the nature of the problem and explains how to identify irregularities in circuits operating in the body-biased condition using standard debug tools with simple modifications. It describes some of the bugs discovered in an actual examination and explains how they were diagnosed by analyzing I-V curve traces and infrared emission microscopy (IREM) images.

The sixth FIB-SEM workshop was held March 1, 2013, in Cambridge, Mass. This article provides a summary of the event along with highlights from the 18 paper presentations.

Scan chains help detect and identify failures in integrated circuits, but they are also susceptible to failure themselves. When scan chains break, it does not necessarily render them useless. Normally, scan chains can be debugged and diagnosed so that they can be fixed or used while masking out vector bits associated with broken or corrupted portions of the chain. This article describes the different ways that scan chains can break and how it tends to affect their performance. It explains how to repair various types of scan chain failures or at least regain partial use for limited testing purposes.

This is the story of how the mainstream Omniprobe FIB lift-out solution was invented and delivered to the market.