This is the second part of an article on molecular electronics. The first part, published in the August 2004 issue of EDFA , discussed the development of molecular devices including nanowires, rectifiers, switches, and transistors. Here, the author describes nontraditional molecular computing architectures based on crosspoint arrays, randomized nanocells, and cellular automata. Challenges associated with interconnect demand, lithography alternatives, and defect tolerance are also discussed.

This article discusses the emergence of nanoelectronics and the effect it may have on semiconductor testing and failure analysis. It describes the different types of quantum effect and molecular electronic devices that have been produced, explaining how they are made, how they work, and the changes that may be required to manufacture and test these devices at scale.

This article examines current research into the building blocks of the nanoscale system and the techniques used to synthesize them. Also explored are some proposed ideas and the challenges associated with integrating these building blocks into molecular nanosystems such as chemically assembled electronic nanocomputers (CAENs).

The electronic device failure analysis community will be instrumental in successfully guiding the industry's transformation in reponse to demand for artificial intelligence capabilities. This editorial outlines the challenge and how the FA community can help address growing needs in this technical area.

This article examines the phenomenon of time-dependent dielectric breakdown (TDDB) in ultrathin gate oxide films and explains why it is no longer considered a catastrophic failure in MOSFET-containing ICs.

Layout sensitivity, a measure of vulnerability to yield loss, typically takes several days to compute for a modern VLSI design. In this article, the authors present and demonstrate a new stochastic model that can significantly expedite the process. The model is based on simple IC layout parameters including wire width, wire spacing, and channel density. The authors explain how they derived the model and how it compares to actual data. They also discuss the causes and effects of open and short defects and define the concepts of critical area and layout sensitivity.

The inverted orientation of a flip-chip packaged die makes it vulnerable to optical attacks from the backside. This article discusses the nature of that vulnerability, assesses the threats posed by optical inspection tools and techniques, and provides insights on effective countermeasures.

Trapped ion systems are one of the leading technology platforms for quantum computing. This article describes the construction and operation of ion trap devices and the various modes of failure that have been observed. Examples of failure in either the rendering or use of packaged trap chips are presented, including electrode shorts and opens, detached bond wires, and RF breakdown damage.

This article reviews recent developments in the area of molecular-scale computing. It describes the construction and operating characteristics of molecular wires, rectifiers, switches, and transistors. It also discusses the concept of molecular gain. Molecular computing architectures based on crosspoint arrays, randomized nanocells, and cellular automata will be discussed in Part II of this article in the November 2004 issue of EDFA .

A new product-like test chip developed by engineers at Carnegie Mellon University overcomes the current limitations in conventional test chip design. This article discusses the advantages of the new chip, called the CM-LCV, and presents experimental results showing how it achieves fault coverages comparable to or better than benchmarking designs.

This article describes a hardware metering fingerprint technique, called the memometer, that addresses supply chain integrity issues with field-programmable gate arrays (FPGAs). The memometer is a physically unclonable function (PUF) based on cross-coupled lookup tables that overcomes manufacturing memory power-on preset. The fingerprints are not only unique, but also reliable with average hamming distances close to the ideal values of 50% (interchip) and 0% (intrachip). Instead of having one fingerprint per device, the memometer makes provision for hundreds with the potential for more.