Unit level traceability (ULT) is a powerful tool that allows complete die histories to be accessed in the course of testing and analysis. It is especially useful for identifying the likely causes of microprocessor failures and in cases where failure analysis resources are limited. In the article, the author explains how he used ULT in the investigation of a 0.25-µm CMOS processor. Using the ULT of the die, he discovered a failure signature based on die location on the wafer. One root cause of failure was traced to cross-field variation in the lithography process due to marginal focus control. Another failure, observed after burn-in, was traced to the presence of residual titanium left after metal etch.

Layout sensitivity, a measure of vulnerability to yield loss, typically takes several days to compute for a modern VLSI design. In this article, the authors present and demonstrate a new stochastic model that can significantly expedite the process. The model is based on simple IC layout parameters including wire width, wire spacing, and channel density. The authors explain how they derived the model and how it compares to actual data. They also discuss the causes and effects of open and short defects and define the concepts of critical area and layout sensitivity.

This article discusses the basic principles of dark current spectroscopy (DCS), a measurement technique that can detect and identify low levels of metal contaminants in CMOS image sensors. An example is given in which DCS is used to determine the concentration of tungsten and gold contaminants in an image sensor and estimate the dark current generated by a single atom of each metal.

This column reflects on the emergence of integrated fabless manufacturers (IFMs) in the semiconductor industry and the effect it will have on failure analysis. In the IFM environment, FA will likely play the same roles, as in design debug, qualification, yield, and customer returns, but with new challenges and expectations as explained in this guest column.

The ratio of good to bad die on a production wafer can range from less than 10% to well over 90%, depending on the process and the complexity of the design. This article provides an overview of the modeling approaches used to predict wafer yield. It explains how to account for relative circuit complexity, systematic and random defects, and defect clustering. As the examples in the article show, with just a basic understanding of yield models, readers can estimate expected yield losses and identify abnormal yield results for a given design.

Optical second-harmonic generation (SHG) is a noninvasive technique that provides information about interface properties and crystal defects. This article demonstrates the use of SGH in the study of high-k dielectrics, silicon-on-insulator structures, compound semiconductors, and through-silicon vias.

Failure analysis is the study and presentation of observable or measurable phenomena. Risk assessment, on the other hand, is when root causes are studied to predict the potential for future failures. In this article, the author describes a structured problem-solving approach that consists of failure analysis, risk assessment, and advanced modeling. A case study is also presented in which the probability of future failures, due to a delamination defect, is determined based on field returns.

Scan-based diagnostics produce high-confidence target lists of suspected faults associated with electrical fail signatures. Physical coordinates extracted from these lists serve as a guide for physical failure analysis. When certain conditions are met for the design database and pattern sets, the extraction can be automated and the analysis completed within minutes. The logic mapping flow is a natural extension of scan-based diagnosis with the potential to reach new levels of electrical failure analysis without the extensive data collection and resources associated with signature analysis. This article describes the logic mapping concept and how to implement the flow. It also presents the results of actual cases in which logic mapping was used.

This article discusses the causes and effects of stuck-open faults (SOFs) in nanometer CMOS ICs. It addresses detection and localization challenges and explains how resistive contacts and vias and the use of damascene-copper processes contribute to the problem. It also discusses layout techniques that reduce the likelihood of SOF failures.

This article discusses the basic principles of SEM-based cathodoluminescence (CL) spectroscopy and demonstrates its usefulness in process development, statistical process control, and failure analysis. The technologies where the benefits of CL spectroscopy are most evident are compound semiconductor optoelectronics and high electron mobility transistors as reflected in the application examples.

Magnetic current imaging provides electrical fault isolation for shorts, leakage currents, resistive opens, and complete opens. In addition, it can be performed nondestructively from either side a die, wafer, packaged IC, or PCB. This article reviews the basic theory and attributes of MCI, describes the types of sensors used, and discusses general measurement procedures. It also presents application examples demonstrating recent advancements and improvements in MCI.

Electromigration is a wearout mechanism that contributes significantly to IC failures. This article discusses the causes and effects of this often overlooked failure mode and presents practical guidelines to help analysts determine whether or not electromigration is the cause of a particular failure. It also discusses the differences between aluminum and copper electromigration.

Failure analysis is becoming increasingly difficult with the emergence of 3D integrated packages due to their complex layouts, diverse materials, shrinking dimensions, and tight fits. This article demonstrates several FA techniques, including high-frequency scanning acoustic microscopy, lock-in thermography, and FIB cross-sectioning in combination with plasma ion etching or laser ablation. Detailed case studies show how the various methods can be used to analyze bonding integrity between different materials, chip-to-chip interface structures, buried interconnect defects, and through-silicon vias at either the device or package level.

Scanning nonlinear dielectric microscopy (SNDM) is a scanning probe technique that measures changes in oscillation frequency between the probe tip and a voltage-biased sample. As the probe moves across the surface of a semiconductor device, the oscillation frequency changes in response to variations in dielectric properties, charge and carrier density, dopant concentration, interface states, or any number of other variables that affect local capacitance. Over the past few years, researchers at Tohoku University have made several improvements in dielectric microscopy, the latest of which is a digital version called time-resolved SNDM (tr-SNDM). Here they describe their new technique and present an application in which it is used to acquire CV, d C /d V-V , and DLTS data from SiO 2 /SiC interface samples.

Laser stimulation is widely used to reveal defects in ICs through either heating or photonic effects. The standard approach is to use lasers with wavelengths above the bandgap wavelength of silicon to create localized heating and below it to generate photocurrent. In practice, most FAs use 1340 nm (IR) lasers for TIVA measurements and either 532 nm (visible) or 1064 nm (near IR) lasers for LIVA analysis. However, as this article demonstrates, visible and near IR lasers can also be used for TIVA analysis and, in some cases, may be preferrable based on signal strength and spatial resolution.

Magnetic current imaging is a proven fault-isolation technique. Its unsurpassed sensitivity and resolution coupled with the fact that magnetic fields are unaffected by packaging and die materials make it a valuable FA tool for a wide variety of ICs and devices. This article reviews the basic measurement physics of magnetic current imaging, describes the general implementation, and presents several practical examples of its use.

This article describes the basic measurement physics of scanning nitrogen vacancy (NV) microscopy and the various ways it can be used in semiconductor device failure analysis. Scanning NV microscopy can measure topography as well as magnetic fields, local current density, ac noise, and local temperature variations.

This article examines current research into the building blocks of the nanoscale system and the techniques used to synthesize them. Also explored are some proposed ideas and the challenges associated with integrating these building blocks into molecular nanosystems such as chemically assembled electronic nanocomputers (CAENs).

This article provides a qualitative overview of several new defect localization techniques, including charge-induced voltage alteration (CIVA), light-induced voltage alteration (LIVA), thermally-induced voltage alteration (TIVA), and Seebeck effect imaging (SEI). It explains how each method works in terms of the physics of signal generation and the types of images they produce. It also includes a summary highlighting the similarities and differences of each technique.

Voltage contrast followed by electron beam induced current imaging is an effective approach for isolating IC failures. This article briefly reviews the physics of signal generation for both techniques and presents several examples illustrating how this powerful combination contributes to advanced defect localization.