The ratio of good to bad die on a production wafer can range from less than 10% to well over 90%, depending on the process and the complexity of the design. This article provides an overview of the modeling approaches used to predict wafer yield. It explains how to account for relative circuit complexity, systematic and random defects, and defect clustering. As the examples in the article show, with just a basic understanding of yield models, readers can estimate expected yield losses and identify abnormal yield results for a given design.

Scanning capacitance microscopy (SCM) and nanoprobing are key tools for isolating and understanding transistor level fails. In this case study, SCM and nanoprobing are used to determine the electrical characteristics of cluster-type failures in 14 nm SOI FinFET SRAM after standard FIB cross-section imaging failed to reveal any visible defects.

This article describes a novel method for improving image resolution achieved using time-resolved photon emission techniques. Instead of directly generating images from photon counting, all detected photons are displayed as a point cloud in 3D space and a new higher-resolution image is generated based on probability density functions associated with photon distributions. Unsupervised learning algorithms identify photon distribution patterns as well as fainter emission sources.

Flat-panel X-ray detectors used in medical imaging applications present a challenge to failure analysts due to the scale of the products, the newness of the technology, and the relatively low production rates compared to ICs. This article explains how existing tools are being adapted to accommodate the size of these detectors and the exotic materials from which they are made. It discusses the types of defects that can occur and how they affect critical detector characteristics. It describes the basic approach for defect localization and physical analysis and presents examples of defects in different areas of a flat-panel X-ray detector.

This article discusses the basic principles of dark current spectroscopy (DCS), a measurement technique that can detect and identify low levels of metal contaminants in CMOS image sensors. An example is given in which DCS is used to determine the concentration of tungsten and gold contaminants in an image sensor and estimate the dark current generated by a single atom of each metal.

This article provides insights into the nature of IDDQ and timing defects and the challenges they present to failure analysts based on the findings of a Sematach study.

This article provides a systematic overview of knowledge-based and machine-learning AI methods and their potential for use in automated testing, defect identification, fault prediction, root cause analysis, and equipment scheduling. It also discusses the role of decision-making rules, image annotations, and ontologies in automated workflows, data sharing, and interoperability.

The Package Innovation Roadmap Council (PIRC) was established as part of the Failure Analysis Technology Roadmap activity at the direction of the EDFAS Board. This column provides an overview of a technical paper by the PIRC that highlights recent innovations, technology gaps, and future development trends in package fault isolation and failure analysis. The paper focuses on three main categories: 1) Artificial intelligence (AI) applications, 2) Sample handling, and 3) FA tool robustness.

Scanning nonlinear dielectric microscopy (SNDM) is a scanning probe technique that measures changes in oscillation frequency between the probe tip and a voltage-biased sample. As the probe moves across the surface of a semiconductor device, the oscillation frequency changes in response to variations in dielectric properties, charge and carrier density, dopant concentration, interface states, or any number of other variables that affect local capacitance. Over the past few years, researchers at Tohoku University have made several improvements in dielectric microscopy, the latest of which is a digital version called time-resolved SNDM (tr-SNDM). Here they describe their new technique and present an application in which it is used to acquire CV, d C /d V-V , and DLTS data from SiO 2 /SiC interface samples.

Unit level traceability (ULT) is a powerful tool that allows complete die histories to be accessed in the course of testing and analysis. It is especially useful for identifying the likely causes of microprocessor failures and in cases where failure analysis resources are limited. In the article, the author explains how he used ULT in the investigation of a 0.25-µm CMOS processor. Using the ULT of the die, he discovered a failure signature based on die location on the wafer. One root cause of failure was traced to cross-field variation in the lithography process due to marginal focus control. Another failure, observed after burn-in, was traced to the presence of residual titanium left after metal etch.

One of the co-chairs of the Case Histories sessions at ISTFA 2012 provides a summary of three papers that demonstrate a solid understanding of the semiconductor FA process. The first paper describes the investigation of fractures in PCB traces, the second paper presents a method for analyzing defects due to implanter charging effects, and the third paper explains how analysts determined the cause of automatic test pattern generation failures concentrated in certain areas of the wafer.

Localizing defects in one-of-a-kind failures can take days, weeks, or even months, after which a detailed physical analysis is conducted to determine the root cause. TEM and STEM play complimentary roles in this process; TEM because of its superior spatial resolution and STEM because it produces images that are easier to interpret and is less susceptible to chromatic aberrations that can occur in thicker samples. In the past, the use of STEM in FA has been limited due to the time required to switch between imaging modes, but with the emergence of TEM/STEM microscopes with computer controlled lenses, the use of STEM is increasing. This article provides an overview of STEM techniques and present examples showing how it is used to characterize subtle and complex defects in ICs.

High-frequency devices such as monolithic microwave ICs (MMICs) are used in telecommunication devices as well as in satellites for earth imaging and radar applications. This article discusses the use of focused ion beam (FIB) cross sectioning and sample decoration techniques for analyzing MMICs and III-V materials.

This article presents a recent breakthrough in the use of machine learning in semiconductor FA. For the first time, cell-internal defects in FinFETs have not only been detected and diagnosed, but also refined, clarified, and resolved using cell-aware diagnosis along with root cause deconvolution (RCD) techniques. The authors describe the development of the methodology and evaluate the incremental improvements made with each step.

This article assesses the capabilities of failure analysis techniques in the context of 65 nm CMOS ICs. It demonstrates the use of OBIRCH, voltage contrast, Seebeck effect imaging, SEM and TEM techniques, and FIB cross-sectioning on failures such as dielectric breakdown, open and resistive vias, voids, shorts, delaminations, and gate oxide defects.

This article discusses the basic principles of SEM-based cathodoluminescence (CL) spectroscopy and demonstrates its usefulness in process development, statistical process control, and failure analysis. The technologies where the benefits of CL spectroscopy are most evident are compound semiconductor optoelectronics and high electron mobility transistors as reflected in the application examples.

Failure analysis is the study and presentation of observable or measurable phenomena. Risk assessment, on the other hand, is when root causes are studied to predict the potential for future failures. In this article, the author describes a structured problem-solving approach that consists of failure analysis, risk assessment, and advanced modeling. A case study is also presented in which the probability of future failures, due to a delamination defect, is determined based on field returns.

This article describes a yield-driven approach for characterizing IC logic failures at the wafer level and presents several case studies to demonstrate its versatility and assess its value.

This article examines current research into the building blocks of the nanoscale system and the techniques used to synthesize them. Also explored are some proposed ideas and the challenges associated with integrating these building blocks into molecular nanosystems such as chemically assembled electronic nanocomputers (CAENs).

Positron spectroscopy can identify defects deep within metals and semiconductors with a resolution better than a single atomic lattice site. This article discusses the basic principles and implementation of positron annihilation spectroscopy and a key development that makes it more a more useful tool for semiconductor applications.