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Journal Articles
EDFA Technical Articles (2004) 6 (1): 13–21.
Published: 01 February 2004
...Lawrence T. Clark; David W. McCarroll; Edward J. Bawolek ICs designed for portable devices often make use of reverse-body bias (RBB) modes to limit leakage currents. The added complexity of RBB support circuitry presents a challenge during IC characterization and debug. This article discusses...
Journal Articles
EDFA Technical Articles (2003) 5 (3): 5–11.
Published: 01 August 2003
...Doug Josephson This article provides a detailed overview of silicon characterization and debug process, describing the intent of each step, the challenges involved, and the FA tools and techniques used. It also discusses the difference between electrical and functional failures, the implementation...
Journal Articles
EDFA Technical Articles (2007) 9 (4): 6–13.
Published: 01 November 2007
...,” was the required tool for IC design debug from the late 1980s to the early 2000s. The history, successes, innovations, mistakes, and possible future of this workhorse tool are visited and described. Copyright © ASM International® 2007 2007 ASM International e-beam probing httpsdoi.org/10.31399/asm.edfa...
Journal Articles
EDFA Technical Articles (2017) 19 (4): 22–34.
Published: 01 November 2017
... 2017 ASM International failure debug circuit validation 2 2 httpsdoi.org/10.31399/asm.edfa.2017-4.p022 EDFAAO (2017) 4:22-34 1537-0755/$19.00 ©ASM International® ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 19 NO. 4 PRODUCT CIRCUIT VALIDATION AND FAILURE DEBUG: A SEMICONDUCTOR FOUNDRY CAN HELP...
Journal Articles
EDFA Technical Articles (2005) 7 (1): 16–24.
Published: 01 February 2005
...Alfred L. Crouch Scan chains help detect and identify failures in integrated circuits, but they are also susceptible to failure themselves. When scan chains break, it does not necessarily render them useless. Normally, scan chains can be debugged and diagnosed so that they can be fixed or used...
Journal Articles
EDFA Technical Articles (2009) 11 (3): 46–47.
Published: 01 August 2009
...Ted Lundquist At a Silicon Valley panel discussion on bringing new ICs to market, there was no mention by anyone onstage of a debug strategy, let alone its importance. This month’s guest columnist offers his insight on why that is and what should be done about it. Copyright © ASM International®...
Journal Articles
EDFA Technical Articles (2000) 2 (4): 13–16.
Published: 01 November 2000
... measure device frequency or cycle time versus voltage. The debug described in this article focused on problems (holes) in Shmoo plots discovered while designing a 637-MHz microprocessor. This problem had two distinct phases as the microprocessor design migrated from an older CMOS process technology...
Journal Articles
EDFA Technical Articles (2011) 13 (4): 4–12.
Published: 01 November 2011
... process, such as at wafer test, before and after packaging, and before and after integration into a complex chip assembly. Thus, methods used to test, debug, and verify multichip modules are generally extensible into the 3-D packaging space. For 3-D silicon integration using through-silicon vias...
Journal Articles
EDFA Technical Articles (2010) 12 (1): 47–48.
Published: 01 February 2010
...Bernard Picart This column describes a unique arrangement between two IC manufacturers that built and share a state-of-the-art failure analysis laboratory. The lab is dedicated to helping the two companies characterize their new technologies, debug new designs, measure IC performance, find defects...
Journal Articles
EDFA Technical Articles (2000) 2 (3): 32–32A.
Published: 01 August 2000
...Jonathan Nall This article explains how antireflection (AR) coatings can improve the results of IR-laser probing when debugging flip-chip ICs from the backside. It discusses the optical physics involved as well as surface preparation requirements. Copyright © ASM International® 2000 2000 ASM...
Journal Articles
EDFA Technical Articles (2000) 2 (3): 20–25.
Published: 01 August 2000
... with backside access to the IC. As the article explains, LVP significantly improves silicon debug and failure analysis throughput time compared to electron-beam probing because it eliminates the need for backside trenching and probe-hole generating operations. Copyright © ASM International® 2000 2000 ASM...
Journal Articles
EDFA Technical Articles (2001) 3 (1): 35–35C.
Published: 01 February 2001
...Rose M. Ring; Rama R. Goruganthu; Leslie Stevenson Flip chip mounted devices are difficult debug using conventional FIB tools because their internal circuitry is not easily accessible. New flip chip focused ion beam (FC FIB) systems overcome this limitation, however, making it possible to access...
Journal Articles
EDFA Technical Articles (2007) 9 (4): 22–25.
Published: 01 November 2007
...John Barden; Joel Harrison Nanoprobing of transistors and resistors is increasing in importance for both design debug and electrical fault isolation. It is thus necessary to understand the impact of scanning a resistor or transistor with an electron beam in order to draw valid conclusions from...
Journal Articles
EDFA Technical Articles (2008) 10 (3): 46–48.
Published: 01 August 2008
...Alan Street This column reflects on the emergence of integrated fabless manufacturers (IFMs) in the semiconductor industry and the effect it will have on failure analysis. In the IFM environment, FA will likely play the same roles, as in design debug, qualification, yield, and customer returns...
Journal Articles
EDFA Technical Articles (2011) 13 (1): 12–19.
Published: 01 February 2011
...) and dual-beam FIB/SEM systems are helping to relieve the pressure with their ability to create site-specific cross sections and to facilitate gate-level circuit rewire and debug. This article reviews the impact of packaging trends on failure analysis along with recent improvements in FIB technology...
Journal Articles
EDFA Technical Articles (2015) 17 (4): 14–20.
Published: 01 November 2015
...Frank Zachariasse; Harry Roberts; Peter van der Cruijsen During a silicon debug, it was found that the gain of a radio receiver circuit dropped dramatically at certain frequencies due to an imbalance in one of the signal paths. A metal fix was proposed, but consensus could not be reached on how...
Journal Articles
EDFA Technical Articles (2014) 16 (3): 20–23.
Published: 01 August 2014
...-flow advice and other recommendations.[1] Historically, FIB circuit edit enables developers to significantly improve the process of debugging and validating fixes or exploring design optimization changes before committing Fig. 1 Multiple connections and cuts for frontside FIB circuit edit 20 Electronic...
Journal Articles
EDFA Technical Articles (2010) 12 (2): 29–32.
Published: 01 May 2010
... mission (Choose One) 1. Extremely 2. Very important important 3. Important 4. Unimportant 1. Non-visible defects (e.g., hot carrier, bias temperature instability, etc.) 25.0% (10) 2. Design for debug and 32.5% (13) analysis (e.g., process, layout, or circuit modifications to enable or enhance debug...
Journal Articles
EDFA Technical Articles (2014) 16 (3): 4–12.
Published: 01 August 2014
... in debug turnaround time. These failing dice are usually selected from a specific wafer with signature or failure modes (hard or soft fails) of interest. Under the current workflow, there are no prior insights into the electrical failure signatures for the entire population of failing dice. There is a lack...
Journal Articles
EDFA Technical Articles (2011) 13 (3): 46–48.
Published: 01 August 2011
... played an important part in our adoption of FA techniques, although by no means has the process been painless. By 2006, we were routinely applying RIL and its photoelectric sister, laser-assisted device alteration (LADA), not only to failure analyses but also to silicon debug cases, and with great effect...