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debug
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Journal Articles
EDFA Technical Articles (2004) 6 (1): 13–21.
Published: 01 February 2004
...Lawrence T. Clark; David W. McCarroll; Edward J. Bawolek ICs designed for portable devices often make use of reverse-body bias (RBB) modes to limit leakage currents. The added complexity of RBB support circuitry presents a challenge during IC characterization and debug. This article discusses...
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ICs designed for portable devices often make use of reverse-body bias (RBB) modes to limit leakage currents. The added complexity of RBB support circuitry presents a challenge during IC characterization and debug. This article discusses the nature of the problem and explains how to identify irregularities in circuits operating in the body-biased condition using standard debug tools with simple modifications. It describes some of the bugs discovered in an actual examination and explains how they were diagnosed by analyzing I-V curve traces and infrared emission microscopy (IREM) images.
Journal Articles
EDFA Technical Articles (2003) 5 (3): 5–11.
Published: 01 August 2003
...Doug Josephson This article provides a detailed overview of silicon characterization and debug process, describing the intent of each step, the challenges involved, and the FA tools and techniques used. It also discusses the difference between electrical and functional failures, the implementation...
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This article provides a detailed overview of silicon characterization and debug process, describing the intent of each step, the challenges involved, and the FA tools and techniques used. It also discusses the difference between electrical and functional failures, the implementation and use of on-chip debugging resources, the important role of schmoo plots.
Journal Articles
EDFA Technical Articles (2007) 9 (4): 6–13.
Published: 01 November 2007
...,” was the required tool for IC design debug from the late 1980s to the early 2000s. The history, successes, innovations, mistakes, and possible future of this workhorse tool are visited and described. Copyright © ASM International® 2007 2007 ASM International e-beam probing httpsdoi.org/10.31399/asm.edfa...
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By providing timing information and throughput as device complexities and operating frequencies were rapidly increasing, the e-beam prober, which integrated CAD navigation and waveform measurements while enabling the user to almost disregard the technology “under the hood,” was the required tool for IC design debug from the late 1980s to the early 2000s. The history, successes, innovations, mistakes, and possible future of this workhorse tool are visited and described.
Journal Articles
EDFA Technical Articles (2017) 19 (4): 22–34.
Published: 01 November 2017
... 2017 ASM International failure debug circuit validation 2 2 httpsdoi.org/10.31399/asm.edfa.2017-4.p022 EDFAAO (2017) 4:22-34 1537-0755/$19.00 ©ASM International® ELECTRONIC DEVICE FAILURE ANALYSIS | VOLUME 19 NO. 4 PRODUCT CIRCUIT VALIDATION AND FAILURE DEBUG: A SEMICONDUCTOR FOUNDRY CAN HELP...
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Faster time-to-production of a new product is the common goal of design houses and foundries. This article demonstrates how foundries can contribute through post silicon validation, which allows design houses to focus on more complicated issues.
Journal Articles
EDFA Technical Articles (2005) 7 (1): 16–24.
Published: 01 February 2005
...Alfred L. Crouch Scan chains help detect and identify failures in integrated circuits, but they are also susceptible to failure themselves. When scan chains break, it does not necessarily render them useless. Normally, scan chains can be debugged and diagnosed so that they can be fixed or used...
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Scan chains help detect and identify failures in integrated circuits, but they are also susceptible to failure themselves. When scan chains break, it does not necessarily render them useless. Normally, scan chains can be debugged and diagnosed so that they can be fixed or used while masking out vector bits associated with broken or corrupted portions of the chain. This article describes the different ways that scan chains can break and how it tends to affect their performance. It explains how to repair various types of scan chain failures or at least regain partial use for limited testing purposes.
Journal Articles
EDFA Technical Articles (2009) 11 (3): 46–47.
Published: 01 August 2009
...Ted Lundquist At a Silicon Valley panel discussion on bringing new ICs to market, there was no mention by anyone onstage of a debug strategy, let alone its importance. This month’s guest columnist offers his insight on why that is and what should be done about it. Copyright © ASM International®...
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At a Silicon Valley panel discussion on bringing new ICs to market, there was no mention by anyone onstage of a debug strategy, let alone its importance. This month’s guest columnist offers his insight on why that is and what should be done about it.
Journal Articles
EDFA Technical Articles (2000) 2 (4): 13–16.
Published: 01 November 2000
... measure device frequency or cycle time versus voltage. The debug described in this article focused on problems (holes) in Shmoo plots discovered while designing a 637-MHz microprocessor. This problem had two distinct phases as the microprocessor design migrated from an older CMOS process technology...
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Shmoo plotting began in the early 1970s and still has wide use in characterizing device performance against various parameters. Typically, Shmoo plots measure device frequency or cycle time versus voltage. The debug described in this article focused on problems (holes) in Shmoo plots discovered while designing a 637-MHz microprocessor. This problem had two distinct phases as the microprocessor design migrated from an older CMOS process technology into a newer, faster one. Resolution of the problem, as the article explains, required advanced DFD/DFT (design for debug/design for test) techniques and FIB circuit edit to resolve.
Journal Articles
EDFA Technical Articles (2011) 13 (4): 4–12.
Published: 01 November 2011
... process, such as at wafer test, before and after packaging, and before and after integration into a complex chip assembly. Thus, methods used to test, debug, and verify multichip modules are generally extensible into the 3-D packaging space. For 3-D silicon integration using through-silicon vias...
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3-D silicon integration is reaching the point where it may be deployed. 3-D silicon integration is different from 3-D packaging in that 3-D packaging involves whole packaged chips, and each chip can still be tested individually throughout the manufacturing and assembly process, such as at wafer test, before and after packaging, and before and after integration into a complex chip assembly. Thus, methods used to test, debug, and verify multichip modules are generally extensible into the 3-D packaging space. For 3-D silicon integration using through-silicon vias, the issue is debug or test access to an individual die in the stack. This article reports on efforts by an IEEE P1838 Working Group to develop a per die standard.
Journal Articles
EDFA Technical Articles (2010) 12 (1): 47–48.
Published: 01 February 2010
...Bernard Picart This column describes a unique arrangement between two IC manufacturers that built and share a state-of-the-art failure analysis laboratory. The lab is dedicated to helping the two companies characterize their new technologies, debug new designs, measure IC performance, find defects...
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This column describes a unique arrangement between two IC manufacturers that built and share a state-of-the-art failure analysis laboratory. The lab is dedicated to helping the two companies characterize their new technologies, debug new designs, measure IC performance, find defects responsible for yield loss, and improve product reliability. In addition to discussing the technical capabilities of the lab, our guest columnist also explains how the lab is funded and managed.
Journal Articles
EDFA Technical Articles (2000) 2 (3): 32–32A.
Published: 01 August 2000
...Jonathan Nall This article explains how antireflection (AR) coatings can improve the results of IR-laser probing when debugging flip-chip ICs from the backside. It discusses the optical physics involved as well as surface preparation requirements. Copyright © ASM International® 2000 2000 ASM...
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This article explains how antireflection (AR) coatings can improve the results of IR-laser probing when debugging flip-chip ICs from the backside. It discusses the optical physics involved as well as surface preparation requirements.
Journal Articles
Laser Voltage Probe (LVP): A Novel Optical Probing Technology for Flip-Chip Packaged Microprocessors
EDFA Technical Articles (2000) 2 (3): 20–25.
Published: 01 August 2000
... with backside access to the IC. As the article explains, LVP significantly improves silicon debug and failure analysis throughput time compared to electron-beam probing because it eliminates the need for backside trenching and probe-hole generating operations. Copyright © ASM International® 2000 2000 ASM...
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Laser voltage probing (LVP), an IR-based technique, facilitates through-silicon signal waveform acquisition and high frequency timing measurements from active p-n junctions on CMOS ICs. The ICs can be in flip-chip as well as wire-bond packages with backside access to the IC. As the article explains, LVP significantly improves silicon debug and failure analysis throughput time compared to electron-beam probing because it eliminates the need for backside trenching and probe-hole generating operations.
Journal Articles
EDFA Technical Articles (2001) 3 (1): 35–35C.
Published: 01 February 2001
...Rose M. Ring; Rama R. Goruganthu; Leslie Stevenson Flip chip mounted devices are difficult debug using conventional FIB tools because their internal circuitry is not easily accessible. New flip chip focused ion beam (FC FIB) systems overcome this limitation, however, making it possible to access...
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Flip chip mounted devices are difficult debug using conventional FIB tools because their internal circuitry is not easily accessible. New flip chip focused ion beam (FC FIB) systems overcome this limitation, however, making it possible to access circuits from the backside through the bulk silicon. In this article, the authors explain how they used the new system to gain access to signal lines for backside waveform acquisition. They also describe some of the procedures they developed to repair and modify flip chip circuits from the backside and prepare cross-section samples from the backside for failure analysis and characterization.
Journal Articles
EDFA Technical Articles (2007) 9 (4): 22–25.
Published: 01 November 2007
...John Barden; Joel Harrison Nanoprobing of transistors and resistors is increasing in importance for both design debug and electrical fault isolation. It is thus necessary to understand the impact of scanning a resistor or transistor with an electron beam in order to draw valid conclusions from...
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Nanoprobing of transistors and resistors is increasing in importance for both design debug and electrical fault isolation. It is thus necessary to understand the impact of scanning a resistor or transistor with an electron beam in order to draw valid conclusions from nanoprobe measurements. In this article, the authors show that exposing samples to electron beams with energies above 4 keV can change the value of diffusion resistors by as much as 30% and that changes can occur at even lower voltages in areas of the sample covered with less material. The article also sheds light on why the changes occur.
Journal Articles
EDFA Technical Articles (2008) 10 (3): 46–48.
Published: 01 August 2008
...Alan Street This column reflects on the emergence of integrated fabless manufacturers (IFMs) in the semiconductor industry and the effect it will have on failure analysis. In the IFM environment, FA will likely play the same roles, as in design debug, qualification, yield, and customer returns...
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This column reflects on the emergence of integrated fabless manufacturers (IFMs) in the semiconductor industry and the effect it will have on failure analysis. In the IFM environment, FA will likely play the same roles, as in design debug, qualification, yield, and customer returns, but with new challenges and expectations as explained in this guest column.
Journal Articles
EDFA Technical Articles (2011) 13 (1): 12–19.
Published: 01 February 2011
...) and dual-beam FIB/SEM systems are helping to relieve the pressure with their ability to create site-specific cross sections and to facilitate gate-level circuit rewire and debug. This article reviews the impact of packaging trends on failure analysis along with recent improvements in FIB technology...
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Packaging integration continues to increase in complexity, driving more samples into FA labs for development support and analysis. For many of the jobs, there is also a need for larger removal volumes, compounding the demand for tool time and throughput. Focused ion beam (FIB) and dual-beam FIB/SEM systems are helping to relieve the pressure with their ability to create site-specific cross sections and to facilitate gate-level circuit rewire and debug. This article reviews the impact of packaging trends on failure analysis along with recent improvements in FIB technology. It also presents examples that illustrate how these new FIB techniques are being applied to solve emerging packaging challenges.
Journal Articles
EDFA Technical Articles (2015) 17 (4): 14–20.
Published: 01 November 2015
...Frank Zachariasse; Harry Roberts; Peter van der Cruijsen During a silicon debug, it was found that the gain of a radio receiver circuit dropped dramatically at certain frequencies due to an imbalance in one of the signal paths. A metal fix was proposed, but consensus could not be reached on how...
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During a silicon debug, it was found that the gain of a radio receiver circuit dropped dramatically at certain frequencies due to an imbalance in one of the signal paths. A metal fix was proposed, but consensus could not be reached on how to validate it because of the difficulty of the FIB edit required and the inherent uncertainty of the approach. In this article, the authors explain how they came up with an alternative approach that proved to be faster, more reliable, and easier to validate than the cut-and-join fix initially proposed. They describe each step of the analog circuit editing process, explaining how they deposit, characterize, and connect matched resistors using focused ion beam techniques.
Journal Articles
EDFA Technical Articles (2014) 16 (3): 20–23.
Published: 01 August 2014
...-flow advice and other recommendations.[1] Historically, FIB circuit edit enables developers to significantly improve the process of debugging and validating fixes or exploring design optimization changes before committing Fig. 1 Multiple connections and cuts for frontside FIB circuit edit 20 Electronic...
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This article discusses recent improvements in FIB circuit edit as well as general uses and optimization techniques.
Journal Articles
EDFA Technical Articles (2010) 12 (2): 29–32.
Published: 01 May 2010
... mission (Choose One) 1. Extremely 2. Very important important 3. Important 4. Unimportant 1. Non-visible defects (e.g., hot carrier, bias temperature instability, etc.) 25.0% (10) 2. Design for debug and 32.5% (13) analysis (e.g., process, layout, or circuit modifications to enable or enhance debug...
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The EDFAS Board of Directors (BOD) has undertaken an initiative to help drive the development of failure analysis methods as leading-edge semiconductor technology approaches the sub-20 nm regime. To streamline efforts and leverage existing work, the BOD recently surveyed its constituency to gauge their opinions on the capability gaps identified by the Sematech councils. This article briefly discusses the methodology of the survey and provides a summary of the responses along with key findings.
Journal Articles
EDFA Technical Articles (2014) 16 (3): 4–12.
Published: 01 August 2014
... in debug turnaround time. These failing dice are usually selected from a specific wafer with signature or failure modes (hard or soft fails) of interest. Under the current workflow, there are no prior insights into the electrical failure signatures for the entire population of failing dice. There is a lack...
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This article describes a yield-driven approach for characterizing IC logic failures at the wafer level and presents several case studies to demonstrate its versatility and assess its value.
Journal Articles
EDFA Technical Articles (2011) 13 (3): 46–48.
Published: 01 August 2011
... played an important part in our adoption of FA techniques, although by no means has the process been painless. By 2006, we were routinely applying RIL and its photoelectric sister, laser-assisted device alteration (LADA), not only to failure analyses but also to silicon debug cases, and with great effect...
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This column provides some thoughts on the cultivation of ideas and the conditions that must exist in a failure analysis laboratory to allow fledgling methods to become deeply rooted, flourishing techniques. As an example, the author recounts the introduction and subsequent development of resistive interconnect localization (RIL) is his lab.
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