Dealing with timing failures in nanometer-scale ICs requires a deeper understanding of critical timing paths, noise mechanisms, process variability, timing rules, and the statistical interaction of random parameter values and distributions. This article examines the factors that affect nanometer timing at both the component and system level. It reviews the timing properties of nanoscale logic gates, latches, edge-triggered flip-flops, clocks and their interconnects, resistive vias, and pipeline structures. It also discusses the challenges involved in determining critical timing paths and the underlying causes of nanometer timing failures.

This article explains how the addition of FIB tunable circuits in critical paths on ICs can alleviate some of the challenges encountered during the implementation of mixed-signal ASICs. It walks readers through the implementation of a particular digital ASIC, explaining where and how FIB tunable circuits were used to overcome difficulties, resolve problems, and realize a fully functional chip that met all system specifications on the first pass of the design.

Laser-assisted device alteration (LADA) is an effective tool for identifying speed-limiting paths in ICs. When implemented with a continuous wave laser, it can reveal where the speed-limiting path resides but not when the slow (or fast) logic transition is occurring. To overcome this limitation, an enhanced version of the technique has been developed. This article discusses the capabilities of the new method, called picosecond time-resolved LADA, and explains how it complements the existing failure analysis toolset, facilitating faster resolution of issues and root-cause identification.

Magnetic current imaging provides electrical fault isolation for shorts, leakage currents, resistive opens, and complete opens. In addition, it can be performed nondestructively from either side a die, wafer, packaged IC, or PCB. This article reviews the basic theory and attributes of MCI, describes the types of sensors used, and discusses general measurement procedures. It also presents application examples demonstrating recent advancements and improvements in MCI.

This article examines some of the major forces reshaping the microelectronics industry. It begins with a summary of how the industry has worked up to now. It then describes the economic, processing, and device physics challenges looming on the horizon and explains how the industry is gearing up to meet them. It also discusses the implications of these changes on failure analysis.

The 1997 National Technology Roadmap for Semiconductors (NTRS) and the 1999 International Technology Roadmap for Semiconductors (ITRS) include chapters outlining metrology needs for the silicon semiconductor industry during the next five years and beyond1. The grand challenges include affordable scaling, new materials and structures, and yield and reliability. Although additional requirements within these categories are detailed, it is often difficult for the analytical specialist or metrology equipment vendor to translate these grand challenges into detailed and meaningful roadmaps for success in analytical applications or instrument development. The path-to-impact of a single metrology activity is not always clear.

CMOS IC failure mechanisms are of three general types: bridge defects, open circuit defects, and parametric related failures. This article summarizes bridge and open-circuit defect properties and provides references for further self-study. Bridge defects are characterized based on location, their significance in terms of logic gates and transistors, and critical resistance for dc logic and timing failures. Open defects are more complex and diverse with six possible failure modes each of which are described in the article.

This ISTFA panel addressed one of FA’s biggest problems: strategic planning. After identifying key factors of communication, costs, and “outside” disciplines, several paths to strategic development were discussed.

3-D silicon integration is reaching the point where it may be deployed. 3-D silicon integration is different from 3-D packaging in that 3-D packaging involves whole packaged chips, and each chip can still be tested individually throughout the manufacturing and assembly process, such as at wafer test, before and after packaging, and before and after integration into a complex chip assembly. Thus, methods used to test, debug, and verify multichip modules are generally extensible into the 3-D packaging space. For 3-D silicon integration using through-silicon vias, the issue is debug or test access to an individual die in the stack. This article reports on efforts by an IEEE P1838 Working Group to develop a per die standard.

Parametric failures are of two general types. One type is due to defects that affect circuit parameters. The other type, which occurs in defect-free parts, is the result of interdie parameter statistical variation. IC failures can be caused by variations in any number of parameters including L eff , W eff , I Dsat , V t , contact resistance, effective gate oxide thickness, source and drain resistance, interconnect sheet resistance, and intrametal spacing affecting cross-talk, ground bounce noise, and IR voltage drops. These failures often influence the maximum operating frequency of the IC and are seldom detected by simple stuck-at fault, delay fault, functional, or I DDQ tests. This article discusses the origin, classification, and detection of a wide range of parametric failures.

This article explains how oxide traps and mobile ions can lead to timing and function failures in ICs and provides insights and advice on how to identify and deal with potential problems.

Semiconductor trends, as embodied in the International Technology Roadmap for Semiconductors (ITRS), provide a guide for the challenges facing the failure analysis community. This process is a risk assessment of key features forecast for the impact of future technologies on failure analysis. The technical challenges fall primarily into two categories: failure site isolation and physical analysis. The failure site isolation challenges are largely driven by the device complexity and reduced accessibility of circuit nets. Additional challenges arise due to the increase in device operating speed and pin count. The challenges in physical analysis are driven primarily by smaller device feature sizes and by the host of new materials being introduced. In addition to the technical challenges, infrastructure changes are also likely to occur. The industry paths for addressing these challenges are discussed.

This column provides some thoughts on the cultivation of ideas and the conditions that must exist in a failure analysis laboratory to allow fledgling methods to become deeply rooted, flourishing techniques. As an example, the author recounts the introduction and subsequent development of resistive interconnect localization (RIL) is his lab.

This article reviews the basic failure modes of surface-mount tantalum capacitors and the methods used to determine the cause. It discusses the factors that contribute to leakage, shorts, opens, and high series resistance, the characteristics of each failure mode, and the best approaches for failure analysis.

This article examines the phenomenon of time-dependent dielectric breakdown (TDDB) in ultrathin gate oxide films and explains why it is no longer considered a catastrophic failure in MOSFET-containing ICs.

This article describes a hardware metering fingerprint technique, called the memometer, that addresses supply chain integrity issues with field-programmable gate arrays (FPGAs). The memometer is a physically unclonable function (PUF) based on cross-coupled lookup tables that overcomes manufacturing memory power-on preset. The fingerprints are not only unique, but also reliable with average hamming distances close to the ideal values of 50% (interchip) and 0% (intrachip). Instead of having one fingerprint per device, the memometer makes provision for hundreds with the potential for more.

This article demonstrates the strengths and limitations of electrical testing for locating defects that contribute to contact failures in DRAMs. It presents three case studies, the first of which involves a write problem to a pair of cells that share an open bitline contact. The second case, a read problem between the primary and secondary sense amplifiers, serves as an example of how failure bitmaps and electrical characterization work together to detect and locate defects. The third case is a decoder problem that required additional testing and internal probing in order to determine the location of the defect.

The failure of a white LED backlight module in a portable computer illustrates the challenges that component and system suppliers must overcome in order to determine root-cause failure mechanisms and take corrective actions that address the problem.

Weak open contacts are common in DRAM cell arrays where they act as a resistance between the cell capacitor and wordline transistor. This article discusses the role of weak open contacts in DRAM failures, the factors that influence their effect on read and write operations, and the complexities involved in assessing potential problems.

This article discusses the primary differences between electrostatic discharge (ESD) and electrical overstress (EOS) and the circumstances under which they occur. It also explains how to differentiate ESD from EOS during failure analysis and how to avoid common misunderstandings and mistakes.