CMOS IC failure mechanisms are of three general types: bridge defects, open circuit defects, and parametric related failures. This article summarizes bridge and open-circuit defect properties and provides references for further self-study. Bridge defects are characterized based on location, their significance in terms of logic gates and transistors, and critical resistance for dc logic and timing failures. Open defects are more complex and diverse with six possible failure modes each of which are described in the article.

Weak open contacts are common in DRAM cell arrays where they act as a resistance between the cell capacitor and wordline transistor. This article discusses the role of weak open contacts in DRAM failures, the factors that influence their effect on read and write operations, and the complexities involved in assessing potential problems.

Dealing with timing failures in nanometer-scale ICs requires a deeper understanding of critical timing paths, noise mechanisms, process variability, timing rules, and the statistical interaction of random parameter values and distributions. This article examines the factors that affect nanometer timing at both the component and system level. It reviews the timing properties of nanoscale logic gates, latches, edge-triggered flip-flops, clocks and their interconnects, resistive vias, and pipeline structures. It also discusses the challenges involved in determining critical timing paths and the underlying causes of nanometer timing failures.

Parametric failures are of two general types. One type is due to defects that affect circuit parameters. The other type, which occurs in defect-free parts, is the result of interdie parameter statistical variation. IC failures can be caused by variations in any number of parameters including L eff , W eff , I Dsat , V t , contact resistance, effective gate oxide thickness, source and drain resistance, interconnect sheet resistance, and intrametal spacing affecting cross-talk, ground bounce noise, and IR voltage drops. These failures often influence the maximum operating frequency of the IC and are seldom detected by simple stuck-at fault, delay fault, functional, or I DDQ tests. This article discusses the origin, classification, and detection of a wide range of parametric failures.

A review of the 2001 edition of the International Technology Roadmap for Semiconductors indicates major obstacles ahead. Of the three basic failure analysis steps—inspection, deprocessing, and fault isolation—the latter is the most at risk, especially physical fault isolation.

At the ISTFA ’99 event, the organizers arranged for the first time a panel discussion on failure analysis related purely to EOS/ESD issues. Each panelist presented their area of expertise followed by two hours of lively exchange with the attendees and among attendees. The panel discussed how to differentiate EOS and ESD failures. These failures are more critical with the industry move to submicron geometries and newer interconnect materials and other processing technologies, such as copper and flip-chip processing.

The tools of the trade in semiconductor failure analysis have advanced rapidly over the past few decades, bringing major improvements in imaging, deprocessing, and materials analysis. In contrast to the progress made in physical FA, little attention has been given to the failure analysis process itself. This article shows through case studies how simple oversights and misunderstandings can lead to costly mistakes. It also defines basic FA concepts and presents a failure analysis sequence, describing each step along with common pitfalls and best practices.

Several technology-focused User's Groups met at ISTFA 2014 to discuss current issues and advances in their areas of interest. This article summarizes key discussion points from the Contactless Fault Isolation User's Group, the Nanoprobing User's Group, the Sample Prep/3-D Package User's Group, and the FIB User's Group.

Magnetic current imaging provides electrical fault isolation for shorts, leakage currents, resistive opens, and complete opens. In addition, it can be performed nondestructively from either side a die, wafer, packaged IC, or PCB. This article reviews the basic theory and attributes of MCI, describes the types of sensors used, and discusses general measurement procedures. It also presents application examples demonstrating recent advancements and improvements in MCI.

Differential Hall effect metrology (DHEM) provides depth profiles of all critical electrical parameters through semiconductor layers at nanometer-level depth resolution. This article describes the relatively new method and shows how it is used to measure mobility and carrier concentration profiles in different materials and structures.

This column provides some thoughts on the cultivation of ideas and the conditions that must exist in a failure analysis laboratory to allow fledgling methods to become deeply rooted, flourishing techniques. As an example, the author recounts the introduction and subsequent development of resistive interconnect localization (RIL) is his lab.

Layout sensitivity, a measure of vulnerability to yield loss, typically takes several days to compute for a modern VLSI design. In this article, the authors present and demonstrate a new stochastic model that can significantly expedite the process. The model is based on simple IC layout parameters including wire width, wire spacing, and channel density. The authors explain how they derived the model and how it compares to actual data. They also discuss the causes and effects of open and short defects and define the concepts of critical area and layout sensitivity.

Resistive interconnections, a type of soft failure, are extremely difficult to find using existing backside methods, and with flip-chip packages, alternative front side approaches are of little or no help. In an effort to address this challenge, a team of engineers developed a new method that uses the effects of resistive heating to directly locate defective vias, contacts, and conductors from either side of the die. In this article, they discuss the basic principles of their new method and demonstrate its use on two ICs in which a variety of resistive interconnection failures were found.

This column provides an update on the latest developments in 3D IC technology and outlines the work that still remains before the promises of full 3D integration can be realized.

Probing in the sub-100 nm realm requires new tools and techniques that are relatively easy to learn if users follow the advice of the authors of this article. The authors present a probing method based on scanning probe technology and demonstrate its use on a 90-nm transistor failure due to a poly-silicon gate short. They also address challenges associated with sample preparation, probe tip contamination and wear, and the effects of vibration and drift.

Laser-assisted device alteration (LADA) is an effective tool for identifying speed-limiting paths in ICs. When implemented with a continuous wave laser, it can reveal where the speed-limiting path resides but not when the slow (or fast) logic transition is occurring. To overcome this limitation, an enhanced version of the technique has been developed. This article discusses the capabilities of the new method, called picosecond time-resolved LADA, and explains how it complements the existing failure analysis toolset, facilitating faster resolution of issues and root-cause identification.

Dynamic laser stimulation is widely used in the PASS/FAIL mapping mode for soft defect localization. Recent improvements, including parametric mapping and multiple-parameter acquisition, significantly increase the amount of information that can be extracted from DLS measurements. This article explains where and how these new techniques are used and how they may be even further improved.

The Assembly Analytical Forum (AAF) is an organization under the auspices of the Sematech Quality Council. The AAF charter is to develop Packaging Analytical Roadmaps five to ten years into the future that are consistent with the International Technology Roadmap for semiconductors (ITRS). At ISTFA 2003, the AAF will convene with interested conference attendees to review, edit, and validate a white paper that will quantify critical gaps in the current suite of test, measurement, and characterization tools used in the semiconductor industry and provide recommendations on how to address them. The intent is to update the document biannually and review it in numerous industry venues to ensure its relevancy and utility. This article is somewhat of a preview to the Rev 0 AAF white paper.

Diagnostic failure analysis tools provide essential information about where a defect is located and what materials are present, but that information must be combined with other data to establish cause and corrective action. Mistakes made at this stage of the investigation can be extremely costly. This article identifies some of the pitfalls and traps that failure analysts can fall into and explains how to avoid them. It provides three examples of misdiagnosed failures and helps readers to see what led analysts astray.

Semiconductor trends, as embodied in the International Technology Roadmap for Semiconductors (ITRS), provide a guide for the challenges facing the failure analysis community. This process is a risk assessment of key features forecast for the impact of future technologies on failure analysis. The technical challenges fall primarily into two categories: failure site isolation and physical analysis. The failure site isolation challenges are largely driven by the device complexity and reduced accessibility of circuit nets. Additional challenges arise due to the increase in device operating speed and pin count. The challenges in physical analysis are driven primarily by smaller device feature sizes and by the host of new materials being introduced. In addition to the technical challenges, infrastructure changes are also likely to occur. The industry paths for addressing these challenges are discussed.