This article presents a comprehensive study of physical inspection and attack methods, describing the approaches typically used by counterfeiters and adversaries as well as the risks and threats created. It also explains how physical inspection methods can serve as trust verification tools and provides practical guidelines for making hardware more secure.

Using the example of smart card radio frequency identification (RFID) devices, this article examines electrostatic discharge risk scenarios encountered during assembly and in the field, and outlines basic countermeasures.

Interposers play an important role in 2.5D and 3D packages, routing power and communication signals between dies while maintaining electrical contact with I/O pins. This role and their relatively simple construction makes interposers a target for malicious attacks. In this article, the authors assess the vulnerabilities inherent in the fabrication of interposers and describe various types of optical attacks along with practical countermeasures.

This article describes how physical attacks can be launched on different types of nonvolatile memory (NVM) cells using failure analysis tools. It explains how the bit information stored inside these devices is susceptible to read-out and fault injection attacks and defines vulnerability parameters to help quantify risks associated with different modalities of attack. It also presents an in-depth security analysis of emerging NVM technologies and discusses potential countermeasures.

The inverted orientation of a flip-chip packaged die makes it vulnerable to optical attacks from the backside. This article discusses the nature of that vulnerability, assesses the threats posed by optical inspection tools and techniques, and provides insights on effective countermeasures.

The organizer and moderator of the ISTFA 2007 panel discussion on failure analysis and testing of medical devices provide a summary of the discussion topics and areas of focus.

This is the second article in a two-part series on the causes of failure in electromechanical relays. Part I, in the February 2018 issue of EDFA , examines a variety of failures caused by the formation of oxide on contact surfaces. As the author explains, electric arcing in the presence of silicon oil or vapor creates SiO 2 deposits in the contact region that build up over time. Here in Part II, the author presents examples of failures caused by nitrous gases, phosphoric acid crystals, and wax, which is often found on enameled copper wires.

It seems that scaling of chip technology according to Moore’s Law will continue for digital functionalities (logic and memory); however, increasing system integration on chip and package levels, called “More than Moore,” has been observed in the past several years. This strong trend in the worldwide semiconductor industry enables more functionality, diversification, and higher value by creating smart microsystems. This article discusses the many challenges faced in FA of 3-D chips, where well-staffed and equipped FA labs are essential. Furthermore, FA is becoming an important strategic enabling factor for new products, not just another “cost factor.”

The 43rd International Symposium for Testing and Failure Analysis (ISTFA 2017) was held in Pasadena, Calif., November 5-9, 2017. This article provides a summary of the keynote presentation, technical program, panel discussion, tutorials, and User’s Group meetings.