Electromigration is a wearout mechanism that contributes significantly to IC failures. This article discusses the causes and effects of this often overlooked failure mode and presents practical guidelines to help analysts determine whether or not electromigration is the cause of a particular failure. It also discusses the differences between aluminum and copper electromigration.

With the introduction of 65 nm technology, the cross-sectional dimensions of copper interconnect in some layers are now smaller than 100 nm, which translates to current densities on the order of several MA/cm2. Electromigration as a root cause for chip failure is thus a major concern and is still being examined. In this article, the authors present recent failure analysis studies on metal-coated copper interconnects, using OBIRCH techniques in combination with FIB cross-sectioning and SEM and TEM imaging.

This article describes an automated sample preparation process for SEM and TEM analysis based on submicron polishing. The method uses robotics, image processing, and a polishing wheel under computer control for a fully automated recipe-driven process that creates exact cross-sections with 0.1 μm accuracy.

Stress voiding has re-emerged as a concern in advanced metal systems with their reduced dimensions and multilayer designs. Unless analysts are familiar with the physics and history of stress voids in ICs, chances are they will go unnoticed. This article discusses the basic cause of stress cracks and the clues that give them away.

A detailed analysis based on FIB etching and SEM image capture was conducted on a flip-chip solder joint deep inside a tablet PC. 3D views reconstructed from SEM images show what appears to be a copper pillar with a solder cap connected to a copper trace on the substrate. The investigators believe the joint was formed by thermal compression bonding with a preapplied underfill. The analysis also revealed the presence of voids and intermetallic compounds along with signs of filler entrapment.

This article discusses the latest trends in wire bonding and examines common failure mechanisms.

The use of a pulsed laser with a lock-in amplifier has been shown to increase the detection sensitivity of scanning optical microscopes by a factor of ten. In this article, the authors explain how they implement laser pulsing without a lock-in amplifier through software control. The detection sensitivity of their method, which is based on a digital signal integration algorithm, has been shown to be comparable to that achieved with a lock-in amplifier. Several case studies illustrate the effectiveness of the technique for locating various types of defects.

Stress voiding is an insidious IC failure mechanism that can be difficult to identify and arrest. It is of particular concern to those who produce and test ICs with aluminum-alloy interconnects or who assess the reliability of legacy devices with long service life. This article explains how stress voids form and grow and how to determine the root cause by amassing physical evidence and ruling out other failure mechanisms. The key to differentiating stress voiding from other types of failures is recognizing that is the result of three distinct physical phenomena, stress, nucleation, and diffusion, all of which must be confirmed before attempting to make process corrections.

This article discusses the causes and effects of stuck-open faults (SOFs) in nanometer CMOS ICs. It addresses detection and localization challenges and explains how resistive contacts and vias and the use of damascene-copper processes contribute to the problem. It also discusses layout techniques that reduce the likelihood of SOF failures.

FIB circuit edit tools and techniques have thus far kept pace with the evolution of interconnect materials in ICs and downward scaling of device dimensions. This article assesses the coming challenges for FIB circuit edit technology and the changes that will be necessary to keep FIB-based etching, milling, and deposition viable in the future.

IBM engineers recently conducted a study to better understand and control the reliability of copper pillar solder joints in 2.5-D packages. Here they describe their approach and the results they obtained. They explain how they created test samples to evaluate different solder compositions, pillar geometries, and thermal histories and assess their effect on microstructure, precipitate morphology, intermetallic layer thickness, and shear strength. They also present thermal cycling test results comparing the performance of silicon and glass interposers.

X-ray tomography has been rapidly gaining acceptance in the semiconductor industry since the first demonstration of its use on IC interconnect in 1999. As failure analysts are discovering, X-ray imaging is more powerful than visible light microscopy and can be used to analyze larger samples than those that fit in an electron microscope. This article provides an introduction to the physics, signal processing, and algorithms involved in X-ray imaging and tomography and the factors that affect resolution.

The 43rd International Symposium for Testing and Failure Analysis (ISTFA 2017) was held in Pasadena, Calif., November 5-9, 2017. This article provides a summary of the keynote presentation, technical program, panel discussion, tutorials, and User’s Group meetings.