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Journal Articles
Failure Analysis of Electronic Material Using Cryogenic FIB-SEM
Available to Purchase
EDFA Technical Articles (2013) 15 (3): 12–19.
Published: 01 August 2013
... techniques provide a solution. It describes the basic setup of a FIB-SEM system and provides examples of its use on InN nanocrystals, GaN films, and copper-containing multilayer photovoltaic materials. FIB milling is difficult if not impossible with III-V compound semiconductors and certain interconnect...
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View articletitled, Failure Analysis of Electronic Material Using Cryogenic FIB-SEM
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for article titled, Failure Analysis of Electronic Material Using Cryogenic FIB-SEM
FIB milling is difficult if not impossible with III-V compound semiconductors and certain interconnect metals because the materials do not react well with the gallium used in most FIB systems. This article discusses the nature of the problem and explains how cryogenic FIB-SEM techniques provide a solution. It describes the basic setup of a FIB-SEM system and provides examples of its use on InN nanocrystals, GaN films, and copper-containing multilayer photovoltaic materials.
Journal Articles
3-D Analysis of a Copper Flip-Chip Interconnection Using FIB-SEM Slice and View
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EDFA Technical Articles (2016) 18 (1): 14–20.
Published: 01 February 2016
.... The analysis also revealed the presence of voids and intermetallic compounds along with signs of filler entrapment. Copyright © ASM International® 2016 2016 ASM International copper pillar bumps FIB-SEM slice and view flip-chip interconnect solder joints 1 4 httpsdoi.org/10.31399/asm.edfa...
Abstract
View articletitled, 3-D Analysis of a <span class="search-highlight">Copper</span> Flip-Chip Interconnection Using FIB-SEM Slice and View
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for article titled, 3-D Analysis of a <span class="search-highlight">Copper</span> Flip-Chip Interconnection Using FIB-SEM Slice and View
A detailed analysis based on FIB etching and SEM image capture was conducted on a flip-chip solder joint deep inside a tablet PC. 3D views reconstructed from SEM images show what appears to be a copper pillar with a solder cap connected to a copper trace on the substrate. The investigators believe the joint was formed by thermal compression bonding with a preapplied underfill. The analysis also revealed the presence of voids and intermetallic compounds along with signs of filler entrapment.
Journal Articles
Accelerated Reliability Testing for Power Semiconductor Packages
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EDFA Technical Articles (2013) 15 (4): 22–25.
Published: 01 November 2013
... illustrates the principal setup of the BST, including specimen design. A crack is initiated at the button-substrate interface, with the selected button having dimensions of 2 mm × 2 mm × 2 mm. For the experimental setup, different molding compounds and substrates are produced, such as copper including typical...
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View articletitled, Accelerated Reliability Testing for Power Semiconductor Packages
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for article titled, Accelerated Reliability Testing for Power Semiconductor Packages
This article describes two accelerated reliability tests that can help shorten product development cycles for power semiconductor packages. One test simulates the effects of temperature cycling by applying a series of thermal shocks to the test sample. The other test assesses the bond between metals and molding compounds as a measure of thermal cycle resistance. A button shear test is used to measure changes in adhesion strength as a function of time and temperature.
Journal Articles
The Copper Challenge to Circuit Edit
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EDFA Technical Articles (2011) 13 (2): 12–18.
Published: 01 May 2011
... metallization etch rates FIB circuit edit iodine compound low-k dielectric httpsdoi.org/10.31399/asm.edfa.2011-2.p012 EDFAAO (2011) 2:12-18 Circuit Editing 1537-0755/$19.00 ©ASM International® The Copper Challenge to Circuit Edit Tahir Malik and Ted Lundquist, DCG Systems [email protected] C...
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View articletitled, The <span class="search-highlight">Copper</span> Challenge to Circuit Edit
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for article titled, The <span class="search-highlight">Copper</span> Challenge to Circuit Edit
The presence of copper layers separated by low-k dielectrics in today’s ICs is a major problem for circuit edit engineers. This article explains why and presents a solution that addresses the challenges CE engineers face. According to the authors, the difficulties are primarily due to the interaction of the ion beam with variations in copper grain orientation, the effects of halogen corrosion, and the presence of CuF. As a result, copper milling tends to be uneven and edit times tend to be quite long. The solution presented is based on a chemically-assisted milling and etching process that quickly and uniformly removes copper and dielectric layers while maintaining planarity.
Journal Articles
Failure Analysis Challenges for Chip-Scale Packages
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EDFA Technical Articles (2013) 15 (2): 14–21.
Published: 01 May 2013
... more difficulty to precision decapsulation. Unlike gold wires, copper wires cannot survive prolonged chemical etch at high temperatures; therefore, low-temperature chemical etch or even a laser-assisted etch must be used as the alternative for removing the mold compound. Compared to a CSP that has...
Abstract
View articletitled, Failure Analysis Challenges for Chip-Scale Packages
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for article titled, Failure Analysis Challenges for Chip-Scale Packages
Chip-scale packages (CSPs) make efficient use of space on PCBs, but their small size, multilevel stacking arrangements, and complex interconnects present serious challenges when it comes to testing and failure analysis. This article describes some of the problems encountered when dealing with various types of CSPs and provides practical solutions based on the tools and techniques available in most FA labs. It discusses the causes and effects of package and die related failures and walks readers through the steps involved in decapsulating plastic FBGA packages using conventional etching, polishing, and milling techniques. It also includes a case study involving a failure caused by improper laser marking.
Journal Articles
Microstructure and Reliability of Tin-Silver Micro-Copper Pillar Assemblies
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EDFA Technical Articles (2018) 20 (1): 20–31.
Published: 01 February 2018
... solder is electroplated on top of a copper pillar. Because of the small volume of solder employed, intermetallic compounds (IMCs) comprise a significant fraction of the resulting solder joint, and very fine Ag3Sn precipitate morphologies can occur. Thus, the microstructure of SnAg solder/ copper pillar...
Abstract
View articletitled, Microstructure and Reliability of Tin-Silver Micro-<span class="search-highlight">Copper</span> Pillar Assemblies
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for article titled, Microstructure and Reliability of Tin-Silver Micro-<span class="search-highlight">Copper</span> Pillar Assemblies
IBM engineers recently conducted a study to better understand and control the reliability of copper pillar solder joints in 2.5-D packages. Here they describe their approach and the results they obtained. They explain how they created test samples to evaluate different solder compositions, pillar geometries, and thermal histories and assess their effect on microstructure, precipitate morphology, intermetallic layer thickness, and shear strength. They also present thermal cycling test results comparing the performance of silicon and glass interposers.
Journal Articles
Enabling True Root Cause Failure Analysis Using an Atmospheric Oxygen-Only Plasma for Decapsulation of Advanced Packages
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EDFA Technical Articles (2021) 23 (1): 4–10.
Published: 01 February 2021
... in this article. In one case, the root cause of failure is chlorine contamination. In another, it is a combination of corrosion and metal migration. The third case involves an EOS failure, the evidence of which was hidden under a layer of carbonized mold compound. In addition to case studies, the article also...
Abstract
View articletitled, Enabling True Root Cause Failure Analysis Using an Atmospheric Oxygen-Only Plasma for Decapsulation of Advanced Packages
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for article titled, Enabling True Root Cause Failure Analysis Using an Atmospheric Oxygen-Only Plasma for Decapsulation of Advanced Packages
Several failure analysis case studies have been conducted over the past few years, illustrating the importance of preserving root-cause evidence by means of artifact-free decapsulation. The findings from three of those studies are presented in this article. In one case, the root cause of failure is chlorine contamination. In another, it is a combination of corrosion and metal migration. The third case involves an EOS failure, the evidence of which was hidden under a layer of carbonized mold compound. In addition to case studies, the article also includes images that compare the results of different decapsulation methods.
Journal Articles
Detrimental Effects of Excessive Gold Plating on Lead-Free Solder Joints
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EDFA Technical Articles (2011) 13 (1): 4–11.
Published: 01 February 2011
...Nausha Asrar This article presents two case histories that shed light on the role of gold in lead-free solder joint failures and the damage mechanisms involved. One of the failures, a brittle fracture of the solder joint, is attributed to the synergistic effects of voids, intermetallic compounds...
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View articletitled, Detrimental Effects of Excessive Gold Plating on Lead-Free Solder Joints
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for article titled, Detrimental Effects of Excessive Gold Plating on Lead-Free Solder Joints
This article presents two case histories that shed light on the role of gold in lead-free solder joint failures and the damage mechanisms involved. One of the failures, a brittle fracture of the solder joint, is attributed to the synergistic effects of voids, intermetallic compounds, and CTE mismatch. The investigation of the other failure revealed evidence of tin-whisker formation. As the author explains, the growth of tin whiskers is due to compressive stress in the tin solder material caused by diffusion of end-cap metals (Ni and Cu) and the formation of Sn-Ni-Au intermetallics. In both cases, the failures can be prevented by limiting the thickness of gold on all components.
Journal Articles
Geolocation of Cu Wires During Sensitive IC Acid Decapsulation
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EDFA Technical Articles (2018) 20 (4): 30–36.
Published: 01 November 2018
... during acid decapsulation. Due to the new epoxy molding compound (EMC) now in widespread use, manual decapsulation is less and less possible. EMC requires a positive pressure that can only be obtained with an acid pump. In addition, the introduction of copper and silver for wires as well as polyimides...
Abstract
View articletitled, Geolocation of Cu Wires During Sensitive IC Acid Decapsulation
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for article titled, Geolocation of Cu Wires During Sensitive IC Acid Decapsulation
Copper wires are susceptible to damage during acid decapsulation and must be protected by stopping the process at the right moment. This article describes the development and evaluation of a method that uses polarization current measurements for end-of-etch detection and subsequent rinse.
Journal Articles
Cleaving Breakthrough: A New Method Removes Old Limitations
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EDFA Technical Articles (2014) 16 (3): 26–31.
Published: 01 August 2014
... itself; the pressure, speed, and location Factor Challenges Sample material Thin samples or brittle ones, such as III-V compound semiconductors, can chip or break unpredictably. For noncrystalline samples, scribing near the edge only chips it and does not initiate a cleave. A sample with many or strong...
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View articletitled, Cleaving Breakthrough: A New Method Removes Old Limitations
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for article titled, Cleaving Breakthrough: A New Method Removes Old Limitations
The scribe-and-cleave method is a widely used sample preparation technique, although numerous challenges make it less than ideal. A new indent-and-cleave approach described in this article provides improved results, even on samples previously considered uncleavable. Several case studies are presented to demonstrate the capabilities of the new technique.
Journal Articles
Emerging Techniques for 3-D Integrated System-in-Package Failure Diagnostics
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EDFA Technical Articles (2012) 14 (2): 14–20.
Published: 01 May 2012
... and 15 m pitch fabricated to test electrical yield, mechanical strength, and reliability of a copper/tincopper bonding process[4] (Fig. 1). The layout of the test vehicle was designed for a 540 × 612 infrared imaging array and provided 256 individual channels of 1272 bumps each, to identify and localize...
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View articletitled, Emerging Techniques for 3-D Integrated System-in-Package Failure Diagnostics
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for article titled, Emerging Techniques for 3-D Integrated System-in-Package Failure Diagnostics
Failure analysis is becoming increasingly difficult with the emergence of 3D integrated packages due to their complex layouts, diverse materials, shrinking dimensions, and tight fits. This article demonstrates several FA techniques, including high-frequency scanning acoustic microscopy, lock-in thermography, and FIB cross-sectioning in combination with plasma ion etching or laser ablation. Detailed case studies show how the various methods can be used to analyze bonding integrity between different materials, chip-to-chip interface structures, buried interconnect defects, and through-silicon vias at either the device or package level.
Journal Articles
Wire Bonding
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EDFA Technical Articles (2016) 18 (1): 22–28.
Published: 01 February 2016
... corrosion. Molding compounds that contain less than 30 ppm chlorine and have a controlled pH of 4 to 6 are now available for copper and are necessary for high-reliability products.[2] Figure 5 shows scanning electron microscopy images of two failure modes that can occur as a result of wire bonding. Normally...
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View articletitled, Wire Bonding
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This article discusses the latest trends in wire bonding and examines common failure mechanisms.
Journal Articles
Nonlinear Optical Characterization of Novel Electronic Materials
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EDFA Technical Articles (2017) 19 (3): 4–11.
Published: 01 August 2017
... structures, compound semiconductors, and through-silicon vias. Copyright © ASM International® 2017 2017 ASM International copper TSVs crystal defects high-k dielectric stacks interface properties optical SHG microscopy second-harmonic generation 4 httpsdoi.org/10.31399/asm.edfa.2017-3...
Abstract
View articletitled, Nonlinear Optical Characterization of Novel Electronic Materials
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for article titled, Nonlinear Optical Characterization of Novel Electronic Materials
Optical second-harmonic generation (SHG) is a noninvasive technique that provides information about interface properties and crystal defects. This article demonstrates the use of SGH in the study of high-k dielectrics, silicon-on-insulator structures, compound semiconductors, and through-silicon vias.
Journal Articles
Failure Mechanisms of Electromechanical Relays on PCBAs: Part II
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EDFA Technical Articles (2018) 20 (2): 4–8.
Published: 01 May 2018
... of silicon oil or vapor creates SiO 2 deposits in the contact region that build up over time. Here in Part II, the author presents examples of failures caused by nitrous gases, phosphoric acid crystals, and wax, which is often found on enameled copper wires. This is the second article in a two-part...
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View articletitled, Failure Mechanisms of Electromechanical Relays on PCBAs: Part II
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for article titled, Failure Mechanisms of Electromechanical Relays on PCBAs: Part II
This is the second article in a two-part series on the causes of failure in electromechanical relays. Part I, in the February 2018 issue of EDFA , examines a variety of failures caused by the formation of oxide on contact surfaces. As the author explains, electric arcing in the presence of silicon oil or vapor creates SiO 2 deposits in the contact region that build up over time. Here in Part II, the author presents examples of failures caused by nitrous gases, phosphoric acid crystals, and wax, which is often found on enameled copper wires.
Journal Articles
Can FIB Circuit Edit Successfully Address Interconnect Trends?
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EDFA Technical Articles (2008) 10 (3): 6–16.
Published: 01 August 2008
... to the required layer thickness. There are compounds containing copper, such as copper hexafluoroacetylacetonate (Cu-hfac), that have been investigated for copper deposition in front-end fab processes. The nonequilibrium environment of sputtering is not supportive of an hfac radical interaction to enable...
Abstract
View articletitled, Can FIB Circuit Edit Successfully Address Interconnect Trends?
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for article titled, Can FIB Circuit Edit Successfully Address Interconnect Trends?
FIB circuit edit tools and techniques have thus far kept pace with the evolution of interconnect materials in ICs and downward scaling of device dimensions. This article assesses the coming challenges for FIB circuit edit technology and the changes that will be necessary to keep FIB-based etching, milling, and deposition viable in the future.
Journal Articles
Site-Specific Analysis of Advanced Packaging Enabled by Focused Ion Beams
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EDFA Technical Articles (2011) 13 (1): 12–19.
Published: 01 February 2011
...Richard J. Young Packaging integration continues to increase in complexity, driving more samples into FA labs for development support and analysis. For many of the jobs, there is also a need for larger removal volumes, compounding the demand for tool time and throughput. Focused ion beam (FIB...
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View articletitled, Site-Specific Analysis of Advanced Packaging Enabled by Focused Ion Beams
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for article titled, Site-Specific Analysis of Advanced Packaging Enabled by Focused Ion Beams
Packaging integration continues to increase in complexity, driving more samples into FA labs for development support and analysis. For many of the jobs, there is also a need for larger removal volumes, compounding the demand for tool time and throughput. Focused ion beam (FIB) and dual-beam FIB/SEM systems are helping to relieve the pressure with their ability to create site-specific cross sections and to facilitate gate-level circuit rewire and debug. This article reviews the impact of packaging trends on failure analysis along with recent improvements in FIB technology. It also presents examples that illustrate how these new FIB techniques are being applied to solve emerging packaging challenges.
Journal Articles
Physical Security Roadmap for Heterogeneous Integration Technology
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EDFA Technical Articles (2022) 24 (2): 24–32.
Published: 01 May 2022
... (C4) to establish an external connection to the interposer. The inter metallic compound (IMC) layer forming between UBM and bumps can potentially cause connection problems and security issues if implemented maliciously. Currently, there are no rigid approaches available to assure the fabrication...
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View articletitled, Physical Security Roadmap for Heterogeneous Integration Technology
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Interposers play an important role in 2.5D and 3D packages, routing power and communication signals between dies while maintaining electrical contact with I/O pins. This role and their relatively simple construction makes interposers a target for malicious attacks. In this article, the authors assess the vulnerabilities inherent in the fabrication of interposers and describe various types of optical attacks along with practical countermeasures.
Journal Articles
Use of a Nuclear Microprobe in Electronic Device Characterization
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EDFA Technical Articles (2007) 9 (4): 14–19.
Published: 01 November 2007
... for each detected element: 70 ppm for chromium; 20 ppm for iron, nickel, and copper; and 100 ppm for zinc, molybdenum, and antimony. The problem for this study was to verify the good ratio of principal components in an AgInSbTe alloy used in Blu-ray Disc rewritable media. Good performance of the material...
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View articletitled, Use of a Nuclear Microprobe in Electronic Device Characterization
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for article titled, Use of a Nuclear Microprobe in Electronic Device Characterization
Microelectronics failure analysis is based on several approaches to study and understand the origin of failure. In addition to “classic” elemental methods (SIMS, ESCA, etc.), there are a number of less-common techniques that can be valuable but require significant equipment investment, specialized operators, and administrative infrastructure to make them available to analysts, if needed. Ion beam analysis methods (RBS, PIXE, NRA), found at the Bordeaux Nuclear Research Center (France), are examples of these specialized tool sets. The capabilities and improved sensitivities of this site for device examination are demonstrated by several examples.
Journal Articles
Tin Whisker Risk Assessment for Space Systems
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EDFA Technical Articles (2012) 14 (1): 14–20.
Published: 01 February 2012
... qualitative model of tin whisker growth, K.N. Tu presented three necessary conditions for spontaneous tin whisker growth in the tin-copper system.[5] First, grain-boundary diffusion of copper in tin must occur. Second, the copper diffusion leads to the formation of copper-tin intermetallic compounds (IMCs...
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View articletitled, Tin Whisker Risk Assessment for Space Systems
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Tin whiskers are single-crystal filaments that can grow from tin-plated copper or nickel components. This article discusses the effect of plating thickness, composition, and grain size on tin whisker formation and explains how to assess damage potential based on microanalysis, whisker length distribution models, and metal vapor arc risk factors. The authors also present and analyze several examples of failures caused by tin whisker formation in space systems.
Journal Articles
A Sample Preparation Workflow for Delayering a 45 nm Node Serial Peripheral Interface Module
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EDFA Technical Articles (2021) 23 (4): 4–13.
Published: 01 November 2021
... etching behavior. As a delayering technique, RIE can be limited by the material of interest particularly if it can contaminate RIE chambers, such as copper, making it difficult to use for fabrication intended systems. The P-FIB is a state-of-the-art dry etching tool that sources ions from a xenon plasma...
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View articletitled, A Sample Preparation Workflow for Delayering a 45 nm Node Serial Peripheral Interface Module
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Further development of SEM-based feature extraction tools for design validation and failure analysis is contingent on reliable sample preparation methods. This article describes how a delayering framework for 130 nm technology was adapted and used on a 45 nm SPI module consisting of 11 metal layers, 10 via layers, two layers of polysilicon, and an active silicon layer. It explains how different polishing and etching methods are used to expose each layer with sufficient contrast for SEM imaging and subsequent feature extraction. By combining polygon sets representing each layer, the full design of the device was reconstructed as shown in one of the images.
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