Search Results for compound semiconductors

FIB milling is difficult if not impossible with III-V compound semiconductors and certain interconnect metals because the materials do not react well with the gallium used in most FIB systems. This article discusses the nature of the problem and explains how cryogenic FIB-SEM techniques provide a solution. It describes the basic setup of a FIB-SEM system and provides examples of its use on InN nanocrystals, GaN films, and copper-containing multilayer photovoltaic materials.

Optical second-harmonic generation (SHG) is a noninvasive technique that provides information about interface properties and crystal defects. This article demonstrates the use of SGH in the study of high-k dielectrics, silicon-on-insulator structures, compound semiconductors, and through-silicon vias.

This article discusses the basic principles of SEM-based cathodoluminescence (CL) spectroscopy and demonstrates its usefulness in process development, statistical process control, and failure analysis. The technologies where the benefits of CL spectroscopy are most evident are compound semiconductor optoelectronics and high electron mobility transistors as reflected in the application examples.

The 1997 National Technology Roadmap for Semiconductors (NTRS) and the 1999 International Technology Roadmap for Semiconductors (ITRS) include chapters outlining metrology needs for the silicon semiconductor industry during the next five years and beyond1. The grand challenges include affordable scaling, new materials and structures, and yield and reliability. Although additional requirements within these categories are detailed, it is often difficult for the analytical specialist or metrology equipment vendor to translate these grand challenges into detailed and meaningful roadmaps for success in analytical applications or instrument development. The path-to-impact of a single metrology activity is not always clear.

This article describes two accelerated reliability tests that can help shorten product development cycles for power semiconductor packages. One test simulates the effects of temperature cycling by applying a series of thermal shocks to the test sample. The other test assesses the bond between metals and molding compounds as a measure of thermal cycle resistance. A button shear test is used to measure changes in adhesion strength as a function of time and temperature.

The scribe-and-cleave method is a widely used sample preparation technique, although numerous challenges make it less than ideal. A new indent-and-cleave approach described in this article provides improved results, even on samples previously considered uncleavable. Several case studies are presented to demonstrate the capabilities of the new technique.

Although plastic-encapsulated packaging dominates most of the IC industry, deprocessing and reliability testing continue to be a problem, particularly in industries making the switch from hermetically sealed ceramic packages. This article discusses the challenges designers and failure analysts face in the military and aerospace electronics industry stemming from the use of plastic packages. It provides examples of the types of failures encountered and describes the procedures used to detect and identify them.

Several failure analysis case studies have been conducted over the past few years, illustrating the importance of preserving root-cause evidence by means of artifact-free decapsulation. The findings from three of those studies are presented in this article. In one case, the root cause of failure is chlorine contamination. In another, it is a combination of corrosion and metal migration. The third case involves an EOS failure, the evidence of which was hidden under a layer of carbonized mold compound. In addition to case studies, the article also includes images that compare the results of different decapsulation methods.

Failure analysis labs are fairly well equipped for dealing with shorts and leakages in stacked-die packages, but are at a disadvantage when it comes to opens, particularly those at the die or die interconnect level. This article presents a new FA technique that has the potential to make up for this shortcoming. The new method, called space domain reflectometry (SDR), is based on radio-frequency magnetic current imaging, and as the authors show, is capable of accurately locating a dead open in a double-stacked BGA package, even when the full stack is encapsulated in molding compound.

Scanning nonlinear dielectric microscopy (SNDM) is a scanning probe technique that measures changes in oscillation frequency between the probe tip and a voltage-biased sample. As the probe moves across the surface of a semiconductor device, the oscillation frequency changes in response to variations in dielectric properties, charge and carrier density, dopant concentration, interface states, or any number of other variables that affect local capacitance. Over the past few years, researchers at Tohoku University have made several improvements in dielectric microscopy, the latest of which is a digital version called time-resolved SNDM (tr-SNDM). Here they describe their new technique and present an application in which it is used to acquire CV, d C /d V-V , and DLTS data from SiO 2 /SiC interface samples.

With the July 2006 implementation of RoHS (the restriction of the use of certain hazardous substances in electrical and electronic equipment), the electronics reliability industry has seen a changeover to lead-free solders and “green” mold compounds that have no bromine- or antimony-based flame retardants. This article addresses some of the challenges caused by implementation of the new requirements.

STEM-EBIC imaging, a nano-characterization technique, has been used in the study of electrically active defects, minority carrier diffusion length, surface recombination velocity, and inhomogeneities in Si pn junctions. In this article, the authors explain how they developed and built a STEM-EBIC system, which they then used to determine the junction location of an InGaN quantum well LED. They also developed a novel FIB-based sample preparation method and a custom sample holder, facilitating the simultaneous collection of Z-contrast, EBIC, and energy dispersive spectroscopy images. The relative position of the pn junction with respect to the quantum well was found to be 19 ± 3 nm from the center of well.

A detailed analysis based on FIB etching and SEM image capture was conducted on a flip-chip solder joint deep inside a tablet PC. 3D views reconstructed from SEM images show what appears to be a copper pillar with a solder cap connected to a copper trace on the substrate. The investigators believe the joint was formed by thermal compression bonding with a preapplied underfill. The analysis also revealed the presence of voids and intermetallic compounds along with signs of filler entrapment.

This article discusses some of the early uses of emission microscopy in semiconductor device failure analysis and the challenges that were overcome to make it the invaluable tool it is today. One of the impediments early on was a misconception that silicon cannot emit light when, in fact, it has several light emission mechanisms that have proven useful in electron microscopy. One such mechanism, avalanche luminescence, occurs in junctions during reverse breakdown and is useful for resolving low breakdown voltage and problems with ESD protection circuits. Other light emission mechanisms discussed in the article include forward bias emission, MOS transistor saturation, and dielectric luminescence, which is used to examine oxide test structures and detect oxide defects.

It seems that scaling of chip technology according to Moore’s Law will continue for digital functionalities (logic and memory); however, increasing system integration on chip and package levels, called “More than Moore,” has been observed in the past several years. This strong trend in the worldwide semiconductor industry enables more functionality, diversification, and higher value by creating smart microsystems. This article discusses the many challenges faced in FA of 3-D chips, where well-staffed and equipped FA labs are essential. Furthermore, FA is becoming an important strategic enabling factor for new products, not just another “cost factor.”

Failure analysis has become a critical enabler of semiconductor technology innovations. Logic and memory scaling continues at an unabated pace with new materials and transistor architectures being introduced. The integration of advanced packaging technologies like chiplets, 2.5D, and 3D in mainstream devices is exploding. To address these challenges, a new industry-wide FA Technology Roadmap was created and approved by the EDFAS Board in 2020. This column discusses the planned next steps in the Roadmap project.

This column is part of a series of reports on the findings to date of the EDFAS Failure Analysis Roadmap Councils. The Failure Analysis Future Roadmap Council (FAFRC) is concerned with identifying the longer term needs of the FA community. This article discusses analysis challenges associated with the growing number of elements being incorporated into integrated circuit fabrication. It includes tables summarizing top challenges in front end and package analysis.

Packaging integration continues to increase in complexity, driving more samples into FA labs for development support and analysis. For many of the jobs, there is also a need for larger removal volumes, compounding the demand for tool time and throughput. Focused ion beam (FIB) and dual-beam FIB/SEM systems are helping to relieve the pressure with their ability to create site-specific cross sections and to facilitate gate-level circuit rewire and debug. This article reviews the impact of packaging trends on failure analysis along with recent improvements in FIB technology. It also presents examples that illustrate how these new FIB techniques are being applied to solve emerging packaging challenges.

The complexity of sample preparation and deprocessing has risen exponentially with the emergence of 2.5-D and 3D packages. This article provides answers and insights on how to deal with the challenges of increasingly complex semiconductor packages. After identifying pressing issues and potential bottlenecks with state-of-the-art FA flows, the authors present two case studies demonstrating the capabilities of electro-optical terahertz pulse reflectometry (EOTPR), plasma FIB milling, and 3D X-ray imaging. The FA results confirm the potential of all three techniques and indicate that a fully nondestructive integration flow for 3D packages may be achievable with further development and optimization.

This article discusses the latest trends in wire bonding and examines common failure mechanisms.