Search Results for circuit validation

Faster time-to-production of a new product is the common goal of design houses and foundries. This article demonstrates how foundries can contribute through post silicon validation, which allows design houses to focus on more complicated issues.

This column discusses the potential benefits of developing a dedicated synchrotron-based tool suite for advanced, high-throughput characterization, deprocessing, and validation of ICs.

During a silicon debug, it was found that the gain of a radio receiver circuit dropped dramatically at certain frequencies due to an imbalance in one of the signal paths. A metal fix was proposed, but consensus could not be reached on how to validate it because of the difficulty of the FIB edit required and the inherent uncertainty of the approach. In this article, the authors explain how they came up with an alternative approach that proved to be faster, more reliable, and easier to validate than the cut-and-join fix initially proposed. They describe each step of the analog circuit editing process, explaining how they deposit, characterize, and connect matched resistors using focused ion beam techniques.

Advanced 10 nm device delayering is a critical process for verifying and validating the circuit design layout and extracting the structures buried inside the chip. The work featured in this article takes advantage of chemically assisted focused ion beam processing with ultraviolet spectroscopy to destructively delayer integrated circuits starting from the shallow trench isolation layer, enabling high-resolution SEM imaging at each layer.

Traditional post-fabrication testing can reliably verify whether or not an IC is working correctly, but it cannot tell the difference between an authentic and counterfeit chip or recognize design changes made with malicious intent. This article presents an IC decomposition workflow, based on FA tools and techniques, that provides a quantifiable level of assurance for components in a zero trust environment.

This article provides an introduction to focused ion beam (FIB) circuit editing, covering the basic process along with best practices and procedures.

This article discusses recent improvements in FIB circuit edit as well as general uses and optimization techniques.

This article discusses the causes and effects of parasitic ringing in the gate drive circuit of dc-to-dc converters. It also presents experimental results validating a possible solution.

Further development of SEM-based feature extraction tools for design validation and failure analysis is contingent on reliable sample preparation methods. This article describes how a delayering framework for 130 nm technology was adapted and used on a 45 nm SPI module consisting of 11 metal layers, 10 via layers, two layers of polysilicon, and an active silicon layer. It explains how different polishing and etching methods are used to expose each layer with sufficient contrast for SEM imaging and subsequent feature extraction. By combining polygon sets representing each layer, the full design of the device was reconstructed as shown in one of the images.

Single contact optical beam induced currents (SCOBIC) is a variation on the OBIC failure analysis technique that requires only one point of contact with the junction being examined. This article discusses the basic principles of this new method and how it compares with OBIC in terms of measurement performance. It also presents examples showing how SCOBIC can be used to analyze CMOS devices from the front and back side without need for complex FIB and microprobing procedures.

The presence of copper layers separated by low-k dielectrics in today’s ICs is a major problem for circuit edit engineers. This article explains why and presents a solution that addresses the challenges CE engineers face. According to the authors, the difficulties are primarily due to the interaction of the ion beam with variations in copper grain orientation, the effects of halogen corrosion, and the presence of CuF. As a result, copper milling tends to be uneven and edit times tend to be quite long. The solution presented is based on a chemically-assisted milling and etching process that quickly and uniformly removes copper and dielectric layers while maintaining planarity.

This article describes a proposed novel metric to furnish chip designers with a prognostic tool for x-ray imaging in the pre-silicon stage. This metric is fashioned to provide designers with a concrete measure of how visible the fine-pitched features of their designs are under x-ray inspection. It utilizes a combination of x-ray image data collection, analysis, and simulations to evaluate different design elements.

By providing timing information and throughput as device complexities and operating frequencies were rapidly increasing, the e-beam prober, which integrated CAD navigation and waveform measurements while enabling the user to almost disregard the technology “under the hood,” was the required tool for IC design debug from the late 1980s to the early 2000s. The history, successes, innovations, mistakes, and possible future of this workhorse tool are visited and described.

This article provides a detailed overview of silicon characterization and debug process, describing the intent of each step, the challenges involved, and the FA tools and techniques used. It also discusses the difference between electrical and functional failures, the implementation and use of on-chip debugging resources, the important role of schmoo plots.

The EDFAS Board of Directors (BOD) has undertaken an initiative to help drive the development of failure analysis methods as leading-edge semiconductor technology approaches the sub-20 nm regime. To streamline efforts and leverage existing work, the BOD recently surveyed its constituency to gauge their opinions on the capability gaps identified by the Sematech councils. This article briefly discusses the methodology of the survey and provides a summary of the responses along with key findings.

Deprocessing of ICs is often the final step for defect validation in FA cases with limited fault-isolation information. This article presents a workflow for deprocessing ICs from the backside using automated thinning and large-area plasma FIB delayering. Advantages to this approach include a reduction in manual planarization and depackaging and a higher degree of precision and repeatability.

Lock-in thermography (LIT) is a widely used nondestructive tool for detecting the failure location in integrated circuits. The image pattern recognition algorithm for detecting LIT hotspots benefits image processing and can be leveraged to automate failure analysis processes.

This article provides a summary of each of the four User’s Group meetings that took place at ISTFA 2011. The summaries cover key participants, presentation topics, and discussion highlights from each of the following groups: Group 1, Focused Ion Beam; Group 2, 3D Packaging and Failure Analysis; Group 3, Finding the Invisible Defect; and Group 4, Nanoprobing and Electrical Characterization.

ICs designed for portable devices often make use of reverse-body bias (RBB) modes to limit leakage currents. The added complexity of RBB support circuitry presents a challenge during IC characterization and debug. This article discusses the nature of the problem and explains how to identify irregularities in circuits operating in the body-biased condition using standard debug tools with simple modifications. It describes some of the bugs discovered in an actual examination and explains how they were diagnosed by analyzing I-V curve traces and infrared emission microscopy (IREM) images.

This paper describes a methodology for preparing contoured devices by using a milling machine in conjunction with a spectral reflectance measurement system for meeting ±5 μm remaining silicon thickness (RST) tolerances.