CMOS IC failure mechanisms are of three general types: bridge defects, open circuit defects, and parametric related failures. This article summarizes bridge and open-circuit defect properties and provides references for further self-study. Bridge defects are characterized based on location, their significance in terms of logic gates and transistors, and critical resistance for dc logic and timing failures. Open defects are more complex and diverse with six possible failure modes each of which are described in the article.

This case study compares the FA success rate and turn-around time of traditional logic-only and true layout-aware scan diagnosis. It discusses the basic process flow, identifies key success factors, and evaluates physical FA and diagnostic test results obtained from six dies randomly selected from a 9.8 M-gate, seven-metal-layer ASIC manufactured in 90 nm technology. As shown, layout-aware diagnosis reduces the defect search area on the die, in some cases, by an order of magnitude, providing the means to diagnosis-driven yield improvements.

Although much traditional FA depends on physical observation to localize failures, electrical techniques are also important, particularly with advances in design for testability (DFT) on modern ICs. DFT structures combined with automated test equipment and algorithmic fault diagnosis facilitate a test-based fault localization (TBFL) approach to identify defect locations on ICs based on scan test patterns. This article and a companion piece in the November 2001 issue of EDFA provide an overview these methods and show how they can reduce the number of potential defect sites on a chip and, in some cases, identify defects that would be missed by other techniques.

Scan-logic diagnosis is used in industry for three main purposes: root-cause analysis, improving manufacturing processes, and improving designs. This article reviews the principles of scan-logic diagnosis and its applications in each of the three areas. It also discusses ongoing challenges and emerging approaches.

Scan-based diagnostics produce high-confidence target lists of suspected faults associated with electrical fail signatures. Physical coordinates extracted from these lists serve as a guide for physical failure analysis. When certain conditions are met for the design database and pattern sets, the extraction can be automated and the analysis completed within minutes. The logic mapping flow is a natural extension of scan-based diagnosis with the potential to reach new levels of electrical failure analysis without the extensive data collection and resources associated with signature analysis. This article describes the logic mapping concept and how to implement the flow. It also presents the results of actual cases in which logic mapping was used.

This article summarizes major discussion points from four User’s Group meetings held at the ISTFA 2009 conference. The topics addressed are "Optical Techniques: Growth and Limitations," "Resolution of Nanoprobing for 45 nm and Beyond: New Challenges," "FIB," and "Fast ASIC Fault Isolation: Efficiency and Accurate Resolution of Software-Based Fault Isolation."

This article reviews the basic principles of scanning acoustic microscopy (SAM) and presents several case studies demonstrating its use in failure analysis and counterfeit detection. The FA case studies show how SAM is used to detect delamination, cracking, and manufacturing defects in ceramic chip capacitors and resistors, voids in a full-bridge rectifier, and a radiation-induced defect in a microprocessor. In cases involving counterfeit ICs, CSAM images reveal the presence of an abnormality on component packages, evidence of relabeling, and popcorn fractures indicative of the use of excessive heat and force to dislodge components from circuit board assemblies.

This is the second article in a two-part series on test-based failure analysis (TBFA). The first article, which appeared in the August 2001 issue of EDFA, discussed the need for automated diagnostics and the general concept of TBFA. This article discusses the steps involved in implementing a TBFA process and addresses the challenges that are likely to be encountered. It explains how to gather data required to link observed behavior to specific faults, how to set up and use fault dictionaries, and how to handle unmodeled as well as bridging faults. It also discusses the use of TBFA with conventional voltage and quiescent current (IDDQ) testing.

This article presents a recent breakthrough in the use of machine learning in semiconductor FA. For the first time, cell-internal defects in FinFETs have not only been detected and diagnosed, but also refined, clarified, and resolved using cell-aware diagnosis along with root cause deconvolution (RCD) techniques. The authors describe the development of the methodology and evaluate the incremental improvements made with each step.

X-ray computed tomography is a noninvasive technique that can reveal the internal structure of objects in three dimensions with spatial resolution down to 50 nm. This article discusses the basic principles of this increasingly important imaging technology and presents examples of its use on various types of defects in semiconductor packages.

A team of semiconductor engineers recently developed a new fault localization method tailored for high-resistance faults. In this article, they discuss the basic principle of the technique and explain how they validated it for various test cases.

High-frequency devices such as monolithic microwave ICs (MMICs) are used in telecommunication devices as well as in satellites for earth imaging and radar applications. This article discusses the use of focused ion beam (FIB) cross sectioning and sample decoration techniques for analyzing MMICs and III-V materials.

Parametric failures are of two general types. One type is due to defects that affect circuit parameters. The other type, which occurs in defect-free parts, is the result of interdie parameter statistical variation. IC failures can be caused by variations in any number of parameters including L eff , W eff , I Dsat , V t , contact resistance, effective gate oxide thickness, source and drain resistance, interconnect sheet resistance, and intrametal spacing affecting cross-talk, ground bounce noise, and IR voltage drops. These failures often influence the maximum operating frequency of the IC and are seldom detected by simple stuck-at fault, delay fault, functional, or I DDQ tests. This article discusses the origin, classification, and detection of a wide range of parametric failures.

This column explains how machine learning is being used to diagnose electrical faults and identify potential hot spots and systematic defects during IC design.

This article explains how the failure of a high-voltage capacitor led to the discovery of an unusual defect. Testing showed that the capacitor shorted due to silver migration, which investigators believe was facilitated by voids in the dielectric that had been present from the time of manufacture. Through some combination of time, electric potential, trapped humidity, and elevated operating temperature, plate material migrated into the voids, creating a short path that led to the failure. Using acoustic images as a guide, the failed capacitor was cross-sectioned, allowing investigators to examine the voids more closely and thereby confirm their theory.

Thin film anomalies cause many device failures but they are often difficult to see. In this article, the authors explain how they found and identified an 8 to 10 nm film of tantalum causing pin shorts in a majority of ASIC modules from a particular lot. Initial attempts to delayer some of the failed modules resulted in the loss of the failure signal. It was then decided to use a focused ion beam to selectively mill through the interlayer dielectric. During milling, a secondary electron image revealed anomalous material between the fingers of a power transistor, which was subsequently identified as tantalum. Such defects, as the authors explain, are common in damascene processes when materials are not properly removed during etching.

The Electronic Device Failure Analysis Society established the Die-Level Post-Isolation Domain Council to provide an overview of the upcoming challenges in this area and guide technique developments for next-generation analytical tools. This column summarizes the findings of the council in the areas of sample preparation, microscopy, nanoprobing, circuit editing, and scanning probe microscopy. It is a preview of the full roadmap document, which is in preparation to be released to the EDFAS community.

The ISTFA 2006 panel discussion focused on the integration of test and failure analysis, a topic that was originally addressed at ISTFA 2000. The goal of this year’s panel was to discuss the improvements made to the integration of test and failure analysis and to explore our capabilities for analyzing future technologies.

Electromigration is a wearout mechanism that contributes significantly to IC failures. This article discusses the causes and effects of this often overlooked failure mode and presents practical guidelines to help analysts determine whether or not electromigration is the cause of a particular failure. It also discusses the differences between aluminum and copper electromigration.

Selecting a fault isolation technique for a particular type of SRAM logic failure requires an understanding of available methods. In this article, the authors review common fault isolation techniques and present several case studies, explaining how they determined which technique to use.